Subject: Re: [PATCH v2] powerpc: add setmaskedbits macros

From: Timur Tabi <[email-masked]>
Date: Thu, 16 Aug 2007 10:26:18 -0500

Kumar Gala wrote:

>>     setmaskedbits_be32(&uccp->gumr_l,
>>         UCC_SLOW_GUMR_L_MODE_QMC | UCC_SLOW_GUMR_L_TDCR_1 |
>>         UCC_SLOW_GUMR_L_RDCR_16,
>>                 UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
>>         UCC_SLOW_GUMR_L_RDCR_MASK);
>>
>>     setmaskedbits_be32(&uccp->gumr_h,
>>         UCC_SLOW_GUMR_H_SUART | UCC_SLOW_GUMR_H_TRX |
>>         UCC_SLOW_GUMR_H_TTX, UCC_SLOW_GUMR_H_RFW);
> 
> Can you also show what the UCC_SLOW* values look like.

The second example is actually a trick that lets me set some bits and clear 
others in one shot, so for the gumr_h register, all of the above values are 
single bits.  I guess that's not a good example.

For gumr_l, we have:

#define UCC_SLOW_GUMR_L_TDCR_MASK	0x00030000
#define UCC_SLOW_GUMR_L_TDCR_32	        0x00030000
#define UCC_SLOW_GUMR_L_TDCR_16	        0x00020000
#define UCC_SLOW_GUMR_L_TDCR_8	        0x00010000
#define UCC_SLOW_GUMR_L_TDCR_1	        0x00000000
#define UCC_SLOW_GUMR_L_RDCR_MASK	0x0000c000
#define UCC_SLOW_GUMR_L_RDCR_32		0x0000c000
#define UCC_SLOW_GUMR_L_RDCR_16	        0x00008000
#define UCC_SLOW_GUMR_L_RDCR_8	        0x00004000
#define UCC_SLOW_GUMR_L_RDCR_1		0x00000000
#define UCC_SLOW_GUMR_L_MODE_MASK	0x0000000F
#define UCC_SLOW_GUMR_L_MODE_BISYNC	0x00000008
#define UCC_SLOW_GUMR_L_MODE_AHDLC	0x00000006
#define UCC_SLOW_GUMR_L_MODE_UART	0x00000004
#define UCC_SLOW_GUMR_L_MODE_QMC	0x00000002

So for example, I could not use setbits32 to set UCC_SLOW_GUMR_L_RDCR_16 (10) 
if it was currently UCC_SLOW_GUMR_L_RDCR_32 (11).

-- 
Timur Tabi
Linux Kernel Developer @ Freescale