From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from Sweeper2.alphanetworks.com (sweeper2.alphanetworks.com [210.202.42.140]) by ozlabs.org (Postfix) with ESMTP id 669EDDDE24 for ; Wed, 12 Nov 2008 01:32:03 +1100 (EST) From: "jay_chen" To: Subject: MPC8349 DMA Date: Tue, 11 Nov 2008 22:16:51 +0800 Message-ID: <0697112B46494D3DB284F1EBA6F65D4E@alphajay> MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_NextPart_000_011E_01C9444B.34D59BA0" List-Id: Linux on Embedded PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , This is a multi-part message in MIME format. ------=_NextPart_000_011E_01C9444B.34D59BA0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii" Hi, I am using 2.6.14.5 and MPC8349. I got some DMA problems with PCI devices. So, I tried to understand the DMA stuff of linux. I have one question about cache coherency. In dma-mapping.h, I found some functions are defined as NULL. For example: #define dma_cache_inv(_start,_size) do { } while (0) #define dma_cache_wback(_start,_size) do { } while (0) #define dma_cache_wback_inv(_start,_size) do { } while (0) #define __dma_alloc_coherent(gfp, size, handle) NULL #define __dma_free_coherent(size, addr) do { } while (0) #define __dma_sync(addr, size, rw) do { } while (0) #define __dma_sync_page(pg, off, sz, rw) do { } while (0) Does this mean that I don't need to take care of cache coherency in MPC83xx platform? So, I could use any range of memory for DMA transferring and the hardware will take care of the cache coherency for me? Thanks a lot. Jay Chen. ------=_NextPart_000_011E_01C9444B.34D59BA0 Content-Transfer-Encoding: quoted-printable Content-Type: text/html; charset="us-ascii"

Hi,

I am using 2.6.14.5=20 and MPC8349.

I got some DMA=20 problems with PCI devices.

So, I tried to=20 understand the DMA stuff of linux.

I have one question=20 about cache coherency.

In dma-mapping.h, I=20 found some functions are defined as NULL.

For=20 example:

#define=20 dma_cache_inv(_start,_size) do { } while (0)
#define=20 dma_cache_wback(_start,_size) do { } while (0)
#define=20 dma_cache_wback_inv(_start,_size) do { } while = (0)

#define=20 __dma_alloc_coherent(gfp, size, handle) NULL
#define=20 __dma_free_coherent(size, addr) do { } while (0)
#define=20 __dma_sync(addr, size, rw) do { } while (0)
#define=20 __dma_sync_page(pg, off, sz, rw) do { } while = (0)

Does this mean that I=20 don't need to take care of cache coherency in MPC83xx=20 platform?

So, I could use any=20 range of memory for DMA transferring and the hardware will take care of = the=20 cache coherency for me?

Thanks a=20 lot.

&nbs= p; = ; = =20 Jay Chen.

------=_NextPart_000_011E_01C9444B.34D59BA0-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from az33egw02.freescale.net (az33egw02.freescale.net [192.88.158.103]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "az33egw02.freescale.net", Issuer "Thawte Premium Server CA" (verified OK)) by ozlabs.org (Postfix) with ESMTPS id 5CDB1DDFA0 for ; Wed, 12 Nov 2008 05:20:16 +1100 (EST) Message-ID: <4919CC7D.2070101@freescale.com> Date: Tue, 11 Nov 2008 12:18:37 -0600 From: Scott Wood MIME-Version: 1.0 To: jay_chen Subject: Re: MPC8349 DMA References: <0697112B46494D3DB284F1EBA6F65D4E@alphajay> In-Reply-To: <0697112B46494D3DB284F1EBA6F65D4E@alphajay> Content-Type: text/plain; charset=UTF-8; format=flowed Cc: linuxppc-embedded@ozlabs.org List-Id: Linux on Embedded PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , jay_chen wrote: > I am using 2.6.14.5 and MPC8349. > I got some DMA problems with PCI devices. > So, I tried to understand the DMA stuff of linux. That's very old; have you tried the latest kernel? > I have one question about cache coherency. > In dma-mapping.h, I found some functions are defined as NULL. > For example: > #define dma_cache_inv(_start,_size) do { } while (0) > #define dma_cache_wback(_start,_size) do { } while (0) > #define dma_cache_wback_inv(_start,_size) do { } while (0) > > #define __dma_alloc_coherent(gfp, size, handle) NULL > #define __dma_free_coherent(size, addr) do { } while (0) > #define __dma_sync(addr, size, rw) do { } while (0) > #define __dma_sync_page(pg, off, sz, rw) do { } while (0) > Does this mean that I don't need to take care of cache coherency in > MPC83xx platform? > So, I could use any range of memory for DMA transferring and the > hardware will take care of the cache coherency for me? Yes, however it's still a good idea to call the DMA functions in case the code gets run on hardware that doesn't have coherent DMA, or that needs special DMA mapping for highmem. Make sure that the PCI bridge is configured to snoop, and that you map your memory as coherence-required (normally not necessary on uniprocessor, but there's some weirdness in the 82xx/83xx PCI controller that requires it). -Scott From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from Sweeper2.alphanetworks.com (sweeper2.alphanetworks.com [210.202.42.140]) by ozlabs.org (Postfix) with ESMTP id 0BA68DDDF0 for ; Wed, 19 Nov 2008 22:14:28 +1100 (EST) From: "jay_chen" To: References: <0697112B46494D3DB284F1EBA6F65D4E@alphajay> <4919CC7D.2070101@freescale.com> Subject: Re: MPC8349 DMA Date: Wed, 19 Nov 2008 19:14:11 +0800 Message-ID: <6440C70E43EB4F019FF76DFFA4297B2D@alphajay> MIME-Version: 1.0 In-Reply-To: <4919CC7D.2070101@freescale.com> Content-Type: text/plain; charset="us-ascii" List-Id: Linux on Embedded PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Thanks for your help. Could you give some hints about how to "map your memory as coherence-required"? Jay Chen... -----Original Message----- From: linuxppc-embedded-bounces+jay_chen=alphanetworks.com@ozlabs.org [mailto:linuxppc-embedded-bounces+jay_chen=alphanetworks.com@ozlabs.org] Sent: Wednesday, November 12, 2008 2:19 AM To: jay_chen Cc: linuxppc-embedded@ozlabs.org Subject: [Spam Mail] Re: MPC8349 DMA jay_chen wrote: > I am using 2.6.14.5 and MPC8349. > I got some DMA problems with PCI devices. > So, I tried to understand the DMA stuff of linux. That's very old; have you tried the latest kernel? > I have one question about cache coherency. > In dma-mapping.h, I found some functions are defined as NULL. > For example: > #define dma_cache_inv(_start,_size) do { } while (0) #define > dma_cache_wback(_start,_size) do { } while (0) #define > dma_cache_wback_inv(_start,_size) do { } while (0) > > #define __dma_alloc_coherent(gfp, size, handle) NULL #define > __dma_free_coherent(size, addr) do { } while (0) #define > __dma_sync(addr, size, rw) do { } while (0) #define > __dma_sync_page(pg, off, sz, rw) do { } while (0) Does this mean that > I don't need to take care of cache coherency in MPC83xx platform? > So, I could use any range of memory for DMA transferring and the > hardware will take care of the cache coherency for me? Yes, however it's still a good idea to call the DMA functions in case the code gets run on hardware that doesn't have coherent DMA, or that needs special DMA mapping for highmem. Make sure that the PCI bridge is configured to snoop, and that you map your memory as coherence-required (normally not necessary on uniprocessor, but there's some weirdness in the 82xx/83xx PCI controller that requires it). -Scott _______________________________________________ Linuxppc-embedded mailing list Linuxppc-embedded@ozlabs.org https://ozlabs.org/mailman/listinfo/linuxppc-embedded From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from az33egw02.freescale.net (az33egw02.freescale.net [192.88.158.103]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "az33egw02.freescale.net", Issuer "Thawte Premium Server CA" (verified OK)) by ozlabs.org (Postfix) with ESMTPS id 4FC7CDDE19 for ; Thu, 20 Nov 2008 03:05:25 +1100 (EST) Message-ID: <49243934.6030208@freescale.com> Date: Wed, 19 Nov 2008 10:05:08 -0600 From: Scott Wood MIME-Version: 1.0 To: jay_chen Subject: Re: MPC8349 DMA References: <0697112B46494D3DB284F1EBA6F65D4E@alphajay> <4919CC7D.2070101@freescale.com> <6440C70E43EB4F019FF76DFFA4297B2D@alphajay> In-Reply-To: <6440C70E43EB4F019FF76DFFA4297B2D@alphajay> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Cc: linuxppc-embedded@ozlabs.org List-Id: Linux on Embedded PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , jay_chen wrote: > Thanks for your help. > Could you give some hints about how to "map your memory as > coherence-required"? The M bit needs to be set in the BATs and PTEs. Current kernels do this; I don't know about really old ones such as 2.6.14. -Scott