Subject: Re: UBIFS problem on MPC8536DS

From: Felix Radensky <[email-masked]>
Date: Mon, 19 Oct 2009 21:39:57 +0200

Scott Wood wrote:
> On Sun, Oct 18, 2009 at 11:38:13AM +0200, Felix Radensky wrote:
>   
>> Hi, Scott
>>
>> Scott Wood wrote:
>>     
>>> On Fri, Oct 16, 2009 at 07:01:43AM +0200, Felix Radensky wrote:
>>>       
>>>> Thanks for confirmation. So the real problem is eLBC ?
>>>> What happens if I access other devices on eLBC (e.g. FPGA)
>>>> simultaneously with NAND or NOR ?
>>>>         
>>> AFAICT, the problem is NAND being accessed simultaneously with anything else
>>> on the eLBC (at least GPCM -- not sure about UPM).  Instead of delaying the
>>> memory-like transaction until the NAND special operation has completed, it
>>> seems to just abort the NAND operation.
>>>
>>> eLBC can't really tell the difference whether you've got NOR or FPGA hooked
>>> up to a GPCM chip select, so the problem should still apply.
>>>
>>>       
>> Can you please provide some code example of synchronizing GPCM and NAND ?
>>     
>
> I don't have any.  It's something that would have to be written.
>   
OK, no problem. I just wanted to get an idea of what should be done.
Should the NOR code poll some eLBC register to wait for completion of
NAND special operation ? Can you tell what register is relevant ?

Thanks.

Felix.