Subject: Re: fsl upm NAND Flash issue without GPIO chip handler

From: Scott Wood <[email-masked]>
Date: Tue, 19 Jan 2010 11:13:16 -0600

nanda wrote:
> We had merged the 2.6.24 

That's pretty old...

> with the FSL based NAND driver,

Which one?  Which chip are you using, and how is NAND attached to it?

> we observed that gpio library is mandatory to be included. We have not included the 
> gpios configured in the dts file as the we don’t have the separate GPIO 
> chip(arch/powepc/boot/dts/board.dts).

What separate GPIO chip?  Which "board.dts" are you looking at?

> After executing the image in the board, we observed the below
> 1) The device ID and manufacture Id was printed as "c0" and "c0" and the 
> error message "No NAND device found!!!". Does it mean it is not 
> accessing the NAND flash and the values read are junk one?
> 2) Processor of the board doesn’t connect the Ready/Busy of the NAND 
> flash through the separate GPIO chip. I mean it is directly connected 
> from GPIO Port C of PIN 15 to the Ready/Busy PIN of the NAND flash. 
> Hence is it necessary to port the gpio specific functions like 
> gpio_request/gpio_free(specified in fsl_upm.c file), instead should we 
> need to configure the PIN par_io_config_pin() for configuration of the 
> PORT C with 15th PIN and set the data value using par_io_data_set() 
> (specified arch/powerpc/sysdev/qe_lib/qe_io.c)

Have you tried pointing the "gpios" property at pin 15 of port C?  The 
whole point of this abstraction is that these connections are described 
in the data, not in the code.

-Scott