Subject: Re: PCI on 834x

From: Gary Thomas <[email-masked]>
Date: Wed, 24 Feb 2010 12:14:48 -0700

On 02/24/2010 11:48 AM, Scott Wood wrote:
> Gary Thomas wrote:
>> Does anyone have experience setting up the PCI controller on
>> the MPC8349? I have it running fine when my system has 128MB
>> or less of main memory, but when I have 256MB or more, it all
>> falls apart :-(
>>
>> Any indication of the pertinent settings would be appreciated.
>
> Check the inbound PCI translation registers, especially PIWARn.

Yes, I set it to 256MB (the size of RAM).
I also set PCI_AR0 to a 512MB window (when it's set to 256, I
get address [segmentation violation] errors when accessing my
devices that end up at the high end of the logical address space)
Finally, I set POCMR0 to a 512MB window (corresponding to PCI_AR0)

In this configuration, my device doesn't seem to be able to
access RAM.  If PIWAR1 is too small, the device just hangs.

=============================== 128MB setup =========================
PIWAR1 = 0xA0055000 | (27-1)
POCMR0 = 0x800F0000
PCIAR0 = 0x80000000 | (28-1)
00:00.0 Power PC: Unknown device 1957:0082 (rev 30)
         Flags: bus master, 66MHz, fast devsel, latency 0
         Memory at cc000000 (32-bit, non-prefetchable) [size=1M]
         Memory at c0000000 (64-bit, prefetchable) [size=128M]
         Memory at <unassigned> (64-bit, non-prefetchable)
         Capabilities: [48] #06 [0000]

00:0b.0 Mass storage controller: Silicon Image, Inc. SiI 3512 [SATALink/SATARaid] Serial ATA Controller (rev 01)
         Subsystem: Silicon Image, Inc. SiI 3512 SATALink Controller
         Flags: bus master, 66MHz, medium devsel, latency 0, IRQ 22
         I/O ports at 1000 [size=8]
         I/O ports at 1008 [size=4]
         I/O ports at 1010 [size=8]
         I/O ports at 1018 [size=4]
         I/O ports at 1020 [size=16]
         Memory at cc180000 (32-bit, non-prefetchable) [size=512]
         [virtual] Expansion ROM at cc100000 [disabled] [size=512K]
         Capabilities: [60] Power Management version 2

00:0c.0 Display controller: Fujitsu Limited. Unknown device 2019 (rev 01)
         Flags: bus master, medium devsel, latency 0, IRQ 19
         Memory at c8000000 (32-bit, non-prefetchable) [size=64M]
=====================================================================

=============================== 256MB setup =========================
PIWAR1 = 0xA0055000 | (28-1)
POCMR0 = 0x800E0000
PCIAR0 = 0x80000000 | (29-1)
00:00.0 Power PC: Unknown device 1957:0082 (rev 30)
         Flags: bus master, 66MHz, fast devsel, latency 0
         Memory at d4000000 (32-bit, non-prefetchable) [size=1M]
         Memory at c0000000 (64-bit, prefetchable) [size=256M]
         Memory at <unassigned> (64-bit, non-prefetchable)
         Capabilities: [48] #06 [0000]

00:0b.0 Mass storage controller: Silicon Image, Inc. SiI 3512 [SATALink/SATARaid] Serial ATA Controller (rev 01)
         Subsystem: Silicon Image, Inc. SiI 3512 SATALink Controller
         Flags: bus master, 66MHz, medium devsel, latency 0, IRQ 22
         I/O ports at 1000 [size=8]
         I/O ports at 1008 [size=4]
         I/O ports at 1010 [size=8]
         I/O ports at 1018 [size=4]
         I/O ports at 1020 [size=16]
         Memory at d4180000 (32-bit, non-prefetchable) [size=512]
         [virtual] Expansion ROM at d4100000 [disabled] [size=512K]
         Capabilities: [60] Power Management version 2

00:0c.0 Display controller: Fujitsu Limited. Unknown device 2019 (rev 01)
         Flags: bus master, medium devsel, latency 0, IRQ 19
         [virtual] Memory at d0000000 (32-bit, non-prefetchable) [size=64M]
=====================================================================

Any ideas what I might be missing?

Thanks

-- 
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Gary Thomas                 |  Consulting for the
MLB Associates              |    Embedded world
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