Jenkins, Clive wrote:
>> Hi, 
>>
>> I'm working on bring up for a new board based on Freescales p2020.
>> I have a programmable FPGA as a PCIe device with a buffer I can
>> write to and from.
>> I want to test  performence for the PCIe bus. 
>> I encountered a problem while doing a DMA between the FPGA & DDR. 
>> The whole buffer  moves  to and from  the device  with out
>> mismatches but with low throughtput. 
>> The thing is that the buffer divided to many transactions of byte
>> size instead of transferring it in a burst. 
>> I must mention that even a buffer of word size, divided in to byte
>> transactions by the DMA (the core can read a word so it seems like
>> the DMA fault.
>> I tried to change the latency timer, max latency, min latency and
>> cache line in the configuration space of both sides of the pcie
>> bus. It didn't help.
>> Do you have an idea what can it be? 
>>
>> Thanks,
>> Natalie. 
>>     
>
> Assuming the P2020 has the usual 85xx-style DMA engine, you may have
> the Band Width Control cleared to 0. This 4-bit field (BWC) restricts
> the transfer size to 2^BWC bytes, for BWC=0,1,..0xa. 0xb-0xe are
> reserved. 0xf disables bandwidth sharing to allow uninterrupted
> transfers from each channel, so if you are using several channels
> one channel can completely lock out other channels. BWC=0x8 at reset
> (2^8 = 256 bytes). See the P2020 manual for more details.
>
> BWC is the field with mask 0x0f000000 in the MR (Master Reset)
> register for the channel (0, 1, 2, 3), at offset 0x100, 0x180, 0x200,
> 0x280 relative to the base of the DMA controller.
>
> Clive
>
>
>   
Hi, Thanks.
I changed the BWC but the transactions are still in a byte size instead 
of burst.
Do you have another idea?

Natalie.