Subject: Re: [RFC][PATCH] Kexec support for PPC440x

From: Sebastian Andrzej Siewior <[email-masked]>
Date: Fri, 03 Jun 2011 15:53:10 +0200

Suzuki Poulose wrote:
>>> The way you setup the 1:1 mapping should be close to what you are 
>>> doing on
>>> kernel entry.Isn't it possible to include the file here and in the entry
>>> code?
> 
>> I will make this change and resend the patch.
> 
> I took a look at the way we do it at kernel entry. It looks more cleaner 
> to leave
> it untouched. Especially, when we add the support for 47x in the future, 
> the code
>  will become more unreadable.
> 
> What do you think ?

So the entry code has one 256MiB mapping, you need 8 of those. Entry goes 
for TLB 63 and you need to be flexible and avoid TLB 63 :).
So after all you don't have that much in common with the entry code. If
you look at the FSL-book code then you will notice that I tried to share
some code.

I don't understand why you don't flip the address space bit. On fsl we
setup the tmp mapping in the "other address" space so we don't have two
mappings for the same address. The entry code could be doing this with STS
bit, I'm not sure.

If you want to keep your tiny mmu flip code instead of merging with the
entry code then please don't put it into a separate file. The only reason
why I did it, is to have the code once since I can't branch to it and I
wanted to share code.

> Thanks
> Suzuki

Sebastian