Subject: Re: [PATCH] powerpc/p1023: set IRQ[4:6, 11] to high level sensitive for PCIe

From: Scott Wood <[email-masked]>
Date: Mon, 7 Nov 2011 12:44:01 -0600

On 11/07/2011 02:32 AM, Roy Zang wrote:
> P1023 external IRQ[4:6, 11] do not pin out, but the interrupts are
> shared with PCIe controller.
> The silicon internally ties the interrupts to L, so change the
> IRQ[4:6,11] to high level sensitive for PCIe.

Some extra commentary on why this works would be nice.

The manual says:

> If a PCI Express INTx interrupt is being used, then the PIC must be configured so that external interrupts
> are level-sensitive (EIVPRn[S] = 1).

and

> In general, these signals should be considered mutually exclusive. If a PCI Express INTx signal is being
> used, the PIC must be configured so that external interrupts are level sensitive (EIVPRn[S] = 1). If an IRQn
> signal is being used as edge-triggered (EIVPRn[S] = 0), the system must not allow inbound PCI Express
> INTx transactions.
>
> Note that it is possible to share IRQn and INTx if the external interrupt is level sensitive; however, if an
> interrupt occurs, the interrupt service routine must poll both the external sources connected to the IRQn
> input and the PCI Express INTx sources to determine from which path the external interrupt came. In any
> case, IRQn should be pulled to the negated state as determined by the associated polarity setting in
> EIVPRn[P].

So it looks like there's some magic whereby the configuration of the
MPIC affects how the PCIe feeds the interrupt in.

Is there (or will there be) an erratum, or anything in the manual
besides not being documented as external interrupts, about these
specific interrupts being tied low in silicon or needing to be active high?

-Scott