Subject: Re: [PATCH 1/5] powerpc/85xx/dts: add third elo3 dma component

From: Hongbo Zhang <[email-masked]>
Date: Mon, 16 Dec 2013 17:12:44 +0800

On 12/13/2013 01:43 PM, Liu Shengzhou-B36685 wrote:
>
>> -----Original Message-----
>> From: Hongbo Zhang [mailto:[email-masked]]
>> Sent: Thursday, December 12, 2013 5:57 PM
>> To: Liu Shengzhou-B36685; [email-masked]; Wood Scott-
>> B07421
>> Subject: Re: [PATCH 1/5] powerpc/85xx/dts: add third elo3 dma component
>>
>> Shengzhou,
>> I canceled my patch http://patchwork.ozlabs.org/patch/295157/ because the
>> original wrong elo3-dma-2.dtsi hadn't been merged.
>> But please pay attention to comments from Scott about my changes of
>> adding 208 for some interrupts, and take some actions if needed, or
>> further discussions.
>>
>> Below comments form Scott:
>> "The FSL MPIC binding should be updated to point out how this works.
>> Technically it's not a change to the binding itself, since it's defined
>> in terms of register offset, but the explanatory text says "So interrupt
>> 0 is at offset 0x0, interrupt 1 is at offset 0x20, and so on." which is
>> not accurate for these new high interrupt numbers."
>>
> Hongbo,
> Could you update FSL MPIC binding as Scott pointed out?

We only need to add more explanatory text after the sentence Scott 
pointed out, like:
"But for some hardwares, the MPIC registers for interrupts are not 
continuous in address,  in such cases, an offset can be added to the 
interrupt number to skip the registers which is not for interrupts."

Scott, is that OK?

Thanks.

> thanks,
> Shengzhou