Subject: Re: question on howto use invalidate_dcache_range

From: Roland Dreier <[email-masked]>
Date: 13 Mar 2003 11:09:00 -0800

Dan> That's a problem in any system design.  Consider what would
    Dan> happen if you had an architecture that was hardware cache
    Dan> coherent.  Software that writes to buffers at any time that
    Dan> is also a DMA target will result in unpredictable behavior.
    Dan> The system design for what you described requires a higher
    Dan> level of shared memory software synchronization as it is
    Dan> exactly the unpredictability that has to be prevented in any
    Dan> SMP design.

I think you misunderstood.  The dirty cache line could be produced by
a write to memory executed long before the DMA is initiated.  In a
hardware cache coherent architecture, the bus controller would just
snoop the CPU's cache and invalidate the dirty cache line.

In any case the current Linux kernel seems to do things the way I
believe is necessary: pci_map_single(...PCI_DMA_FROMDEVICE)
invalidates the cache (and is done _before_ the DMA is initiated),
while pci_unmap_single() is a NOOP.

 - Roland

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