Subject: Re: [PATCH] cxl: fix setting of _PAGE_USER bit when handling page faults

From: Andrew Donnellan <[email-masked]>
Date: Mon, 21 Mar 2016 15:38:39 +1100

On 18/03/16 17:30, Ian Munsie wrote:
> Excerpts from andrew.donnellan's message of 2016-03-18 15:01:21 +1100:
>> Fixes: f204e0b8cedd ("cxl: Driver code for powernv PCIe based cards for
>> userspace access")
>
> It doesn't fix that since there was no cxl kernel API support at the
> time, so this wasn't a regression - just something we missed when the
> kernel api was added (I believe the broken test in the code was a left
> over from some early bringup work and would never have been exercised on
> an upstream kernel until then).

Ah, fair enough - I just looked at what git blame told me. You're right, 
it's not a fix to that commit per se. Happy to drop this tag.

> We haven't run into any problems because of this that I am aware of - do
> we have a test case for this?

I'd be surprised if it caused noticeable problems - the presence of the 
_PAGE_USER bit when it's not necessary shouldn't break anything, as 
opposed to the absence of _PAGE_USER when it is necessary. Not entirely 
sure what the test case would be.

>
>> -    if ((!ctx->kernel) || ~(dar & (1ULL << 63)))
>> +    if ((!ctx->kernel) || !(dar & (1ULL << 63)))
>
> Should it be the top two bits?

benh told me that the top bit should be enough - anything above 0x8000* 
should be kernel space.

-- 
Andrew Donnellan              Software Engineer, OzLabs
[email-masked]  Australia Development Lab, Canberra
+61 2 6201 8874 (work)        IBM Australia Limited