Subject: Re: [PATCH] spapr: Don't set the TM ibm,pa-features bit in PR KVM mode

From: Alexey Kardashevskiy <[email-masked]>
Date: Tue, 5 Apr 2016 17:33:27 +1000

On 04/05/2016 02:09 PM, David Gibson wrote:
> On Tue, Apr 05, 2016 at 12:12:01PM +1000, Paul Mackerras wrote:
>> On Mon, Apr 04, 2016 at 09:09:28PM +1000, Anton Blanchard wrote:
>>> We don't support transactional memory in PR KVM, so don't tell
>>> the OS that we do.
>>
>> This assumes PR KVM won't ever support TM, which is hopefully not
>> true.  If PR KVM does get TM support in future, then QEMU will have no
>> clear way to know whether it needs to clear the pa-features bit or
>> not.  I think we need to define some way for the KVM implementation to
>> tell qemu which of these kinds of CPU features it supports.
>
> Yeah, I think we need some sort of capability flag for this.  We also
> need to isolate this KVM capability testing better into the KVM code,
> so we won't break things on TCG.
>
> Speaking of which... I don't imagine we implement TM instructions in
> TCG either, so we should probably make sure TM isn't advertised there
> either.

TM is "supported" in TCG:

56a846157 "target-ppc: Introduce TM Noops"
===
     Add degenerate implementations of the non-privileged Transactional
     Memory instructions tend., tabort*. and tsr.  This implementation
     simply checks the MSR[TM] bit and then sets CR0 to 0b0000.  This
     is a reasonable degenerate implementation since transactions are
     never allowed to begin and hence MSR[TS] is always 0b00.

     Signed-off-by: Tom Musta <[email-masked]>
     Signed-off-by: Alexander Graf <[email-masked]>
===

-- 
Alexey