Subject: Re: [PATCH V2 23/68] powerpc/mm: Make page table size a variable

From: Balbir Singh <[email-masked]>
Date: Wed, 20 Apr 2016 16:21:46 +1000

On 17/04/16 20:27, Aneesh Kumar K.V wrote:
> Balbir Singh <[email-masked]> writes:
> 
>>> index 2f818cbd8aa6..dcb9d6e94a0c 100644
>>> --- a/arch/powerpc/include/asm/book3s/64/hash-4k.h
>>> +++ b/arch/powerpc/include/asm/book3s/64/hash-4k.h
>>> @@ -5,48 +5,20 @@
>>>   * for each page table entry.  The PMD and PGD level use a 32b record for
>>>   * each entry by assuming that each entry is page aligned.
>>>   */
>>> -#define PTE_INDEX_SIZE  9
>>> -#define PMD_INDEX_SIZE  7
>>> -#define PUD_INDEX_SIZE  9
>>> -#define PGD_INDEX_SIZE  9
>>> +#define H_PTE_INDEX_SIZE  9
>>> +#define H_PMD_INDEX_SIZE  7
>>> +#define H_PUD_INDEX_SIZE  9
>>> +#define H_PGD_INDEX_SIZE  9
>>>  
>>
>> Any comments on where these numbers came from?
>>
>> From these numbers for 4K pages we have
>>
>> Each PMD is 2M
>> Each PUD is 256M
>> Each PGD is 128G
> 
> I am not sure I understand. We are updating linux page table details for
> hash config here. This patch doesn't make any functionality change, it
> just make sure few #defines are marked as a variable.
> 

I was just stating that we need some comments about why we chose a particular
split. It just helps to understand that we use. My comment was just stating
that we need some additional comments and not necessarily due to your change

Balbir