Subject: Re: [PATCH V10 00/28] Add new powerpc specific ELF core notes

From: Laurent Dufour <[email-masked]>
Date: Thu, 21 Apr 2016 18:00:01 +0200

On 13/04/2016 07:14, Michael Ellerman wrote:
> On Mon, 2016-04-11 at 09:40 +0200, Laurent Dufour wrote:
>> On 07/04/2016 23:49, Michael Ellerman wrote:
>>> On 7 April 2016 7:23:46 pm AEST, Laurent Dufour <[email-masked]> wrote:
>>>> This series is required to handle TM state in CRIU.
>>>> Is there a chance to get it upstream soon ?
>>>
>>> We were waiting on the gdb support to make sure it had some testing. If it's working for CRIU that would be a good data point, have you actually tested it with CRIU?
>>
>> I just started integrating it in CRIU, my basic tests didn't report any
>> issue with the new ptrace API, but I can't state that it is bug free ;)
> 
> Sure. But if it's working for CRIU that's at least postive :)

I did additional tests and the Anshuman's series is working fine for
CRIU's support with the attached patch applied.

Michael, could you please applied the attached patch among the
Anshuman's series ?

Thanks,
Laurent.

>>From 7a4f07c54afdbe7bef84d1f700ab9262f449513a Mon Sep 17 00:00:00 2001
From: Laurent Dufour <[email-masked]>
Date: Mon, 11 Apr 2016 18:59:16 +0200
Subject: [PATCH] ppc64: allow ptrace to set TM bits

This patch allows the MSR bits relative to the Transactional memory
state to be manipulated through the ptrace API.

However, in the case the TM available bit is not set in the
manipulated MSR, the changes are ignored.

When dealing with the checkpointed MSR, we must be sure that the TM
state bits will not be set since the checkpointed state can't be a
transactional one.

Signed-off-by: Laurent Dufour <[email-masked]>
---
 arch/powerpc/kernel/ptrace.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index b063fc499c1d..5c792f0bf1ca 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -161,8 +161,12 @@ const char *regs_query_register_name(unsigned int offset)
 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 #define MSR_DEBUGCHANGE	0
 #else
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+#define MSR_DEBUGCHANGE	(MSR_TS_MASK | MSR_SE | MSR_BE)
+#else
 #define MSR_DEBUGCHANGE	(MSR_SE | MSR_BE)
 #endif
+#endif
 
 /*
  * Max register writeable via put_reg
@@ -180,6 +184,12 @@ static unsigned long get_user_msr(struct task_struct *task)
 
 static int set_user_msr(struct task_struct *task, unsigned long msr)
 {
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+	if (!(task->thread.regs->msr & MSR_TM)) {
+		/* If TM is not available, discard TM bits changes */
+		msr &= ~(MSR_TM | MSR_TS_MASK);
+	}
+#endif
 	task->thread.regs->msr &= ~MSR_DEBUGCHANGE;
 	task->thread.regs->msr |= msr & MSR_DEBUGCHANGE;
 	return 0;
@@ -193,6 +203,7 @@ static unsigned long get_user_ckpt_msr(struct task_struct *task)
 
 static int set_user_ckpt_msr(struct task_struct *task, unsigned long msr)
 {
+	msr &= ~MSR_TS_MASK;	/* Checkpoint state can't be in transaction */
 	task->thread.ckpt_regs.msr &= ~MSR_DEBUGCHANGE;
 	task->thread.ckpt_regs.msr |= msr & MSR_DEBUGCHANGE;
 	return 0;
-- 
1.9.1