Subject: Re: [PATCH] powerpc/mm: Update set_ptes to call pte_filter for all the ptes

From: "Aneesh Kumar K.V" <[email-masked]>
Date: Wed, 18 Oct 2023 15:30:37 +0530

Aneesh Kumar K V <[email-masked]> writes:

> On 10/18/23 11:25 AM, Christophe Leroy wrote:
>> 
>> 
>> Le 18/10/2023 à 06:55, Aneesh Kumar K.V a écrit :
>>> With commit 9fee28baa601 ("powerpc: implement the new page table range
>>> API") we added set_ptes to powerpc architecture but the implementation
>>> missed calling the pte filter for all the ptes we are setting in the
>>> range. set_pte_filter can be used for filter pte values and on some
>>> platforms which don't support coherent icache it clears the exec bit so
>>> that we can flush the icache on exec fault
>>>
>>> The patch also removes the usage of arch_enter/leave_lazy_mmu() because
>>> set_pte is not supposed to be used when updating a pte entry. Powerpc
>>> architecture uses this rule to skip the expensive tlb invalidate which
>>> is not needed when you are setting up the pte for the first time. See
>>> commit 56eecdb912b5 ("mm: Use ptep/pmdp_set_numa() for updating
>>> _PAGE_NUMA bit") for more details
>>>
>>> Fixes: 9fee28baa601 ("powerpc: implement the new page table range API")
>>> Signed-off-by: Aneesh Kumar K.V <[email-masked]>
>>> ---
>>>   arch/powerpc/mm/pgtable.c | 33 ++++++++++++++++++++-------------
>>>   1 file changed, 20 insertions(+), 13 deletions(-)
>>>
>>> diff --git a/arch/powerpc/mm/pgtable.c b/arch/powerpc/mm/pgtable.c
>>> index 3ba9fe411604..95ab20cca2da 100644
>>> --- a/arch/powerpc/mm/pgtable.c
>>> +++ b/arch/powerpc/mm/pgtable.c
>>> @@ -191,28 +191,35 @@ void set_ptes(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
>>>   		pte_t pte, unsigned int nr)
>>>   {
>>>   	/*
>>> -	 * Make sure hardware valid bit is not set. We don't do
>>> -	 * tlb flush for this update.
>>> +	 * We don't need to call arch_enter/leave_lazy_mmu_mode()
>>> +	 * because we expect set_ptes to be only be used on not present
>>> +	 * and not hw_valid ptes. Hence there is not translation cache flush
>>> +	 * involved that need to be batched.
>>>   	 */
>>> -	VM_WARN_ON(pte_hw_valid(*ptep) && !pte_protnone(*ptep));
>>> +	for (;;) {
>>>   
>>> -	/* Note: mm->context.id might not yet have been assigned as
>>> -	 * this context might not have been activated yet when this
>>> -	 * is called.
>>> -	 */
>>> -	pte = set_pte_filter(pte);
>>> +		/*
>>> +		 * Make sure hardware valid bit is not set. We don't do
>>> +		 * tlb flush for this update.
>>> +		 */
>>> +		VM_WARN_ON(pte_hw_valid(*ptep) && !pte_protnone(*ptep));
>>>   
>>> -	/* Perform the setting of the PTE */
>>> -	arch_enter_lazy_mmu_mode();
>>> -	for (;;) {
>>> +		/* Note: mm->context.id might not yet have been assigned as
>>> +		 * this context might not have been activated yet when this
>>> +		 * is called.
>>> +		 */
>>> +		pte = set_pte_filter(pte);
>> 
>> Why do you need to call set_pte_filter() inside the loop ?
>> The only difference between previous pte and next pte is the RPN, other 
>> flags remain untouched so I can't see why you need to call 
>> set_pte_filter() again.
>> 
>
> I missed the fact that we use the filtered pte in all the ptes in the range. One other details
> that made me look at calling the filter in the loop was we clearing the struct page->flags.
> The only flag right now we care about the PG_dcache_clean and that moved to folio. So we might be
> good here. May be we add a comment in set_pte_filter saying can operate only on folio->flags ? 
>
>>> +
>>> +		/* Perform the setting of the PTE */
>>>   		__set_pte_at(mm, addr, ptep, pte, 0);
>>>   		if (--nr == 0)
>>>   			break;
>>>   		ptep++;
>>> -		pte = __pte(pte_val(pte) + (1UL << PTE_RPN_SHIFT));
>>>   		addr += PAGE_SIZE;
>>> +		/* increment the pfn */
>>> +		pte = __pte(pte_val(pte) + PAGE_SIZE);
>> 
>> PAGE_SIZE doesn't work on all platforms, see for instance e500.
>> 
>> see comment at 
>> https://elixir.bootlin.com/linux/v6.3-rc2/source/arch/powerpc/include/asm/nohash/32/pgtable.h#L147
>> 
>> And then you see 
>> https://elixir.bootlin.com/linux/v6.3-rc2/source/arch/powerpc/include/asm/nohash/pte-e500.h#L63
>> 
>
> Didn't know that. I actually wanted to do pfn_pte(pte_pfn(pte) + 1) . But that needs pgprot_t. I
> can move it back to PTE_RPN_SHIFT with details of the above documented. 
>

something like this ?

>From 62825870d4b48ffb53e9837dfb4cf7c0422732ec Mon Sep 17 00:00:00 2001
From: "Aneesh Kumar K.V" <[email-masked]>
Date: Fri, 6 Oct 2023 22:47:00 +0530
Subject: [PATCH] powerpc/mm: Avoid calling arch_enter/leave_lazy_mmu() in
 set_ptes

With commit 9fee28baa601 ("powerpc: implement the new page table range
API") we added set_ptes to powerpc architecture. The implementation
included calling arch_enter/leave_lazy_mmu() calls.

The patch removes the usage of arch_enter/leave_lazy_mmu() because
set_pte is not supposed to be used when updating a pte entry. Powerpc
architecture uses this rule to skip the expensive tlb invalidate which
is not needed when you are setting up the pte for the first time. See
commit 56eecdb912b5 ("mm: Use ptep/pmdp_set_numa() for updating
_PAGE_NUMA bit") for more details

The patch also makes sure we are not using the interface to update a
valid/present pte entry by adding VM_WARN_ON check all the ptes we
are setting up. Furthermore, we add a comment to set_pte_filter to
clarify it can only update folio-related flags and cannot filter
pfn specific details in pte filtering.

Removal of arch_enter/leave_lazy_mmu() also will avoid nesting of
these functions that are not supported. For ex:

remap_pte_range()
  -> arch_enter_lazy_mmu()
  -> set_ptes()
      -> arch_enter_lazy_mmu()
      -> arch_leave_lazy_mmu()
  -> arch_leave_lazy_mmu()

Fixes: 9fee28baa601 ("powerpc: implement the new page table range API")
Signed-off-by: Aneesh Kumar K.V <[email-masked]>
---
 arch/powerpc/mm/pgtable.c | 32 ++++++++++++++++++++++----------
 1 file changed, 22 insertions(+), 10 deletions(-)

diff --git a/arch/powerpc/mm/pgtable.c b/arch/powerpc/mm/pgtable.c
index 3ba9fe411604..4d69bfb9bc11 100644
--- a/arch/powerpc/mm/pgtable.c
+++ b/arch/powerpc/mm/pgtable.c
@@ -104,6 +104,8 @@ static pte_t set_pte_filter_hash(pte_t pte) { return pte; }
 /* Embedded type MMU with HW exec support. This is a bit more complicated
  * as we don't have two bits to spare for _PAGE_EXEC and _PAGE_HWEXEC so
  * instead we "filter out" the exec permission for non clean pages.
+ *
+ * This is also called once for the folio. So only work with folio->flags here.
  */
 static inline pte_t set_pte_filter(pte_t pte)
 {
@@ -190,29 +192,39 @@ static pte_t set_access_flags_filter(pte_t pte, struct vm_area_struct *vma,
 void set_ptes(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
 		pte_t pte, unsigned int nr)
 {
-	/*
-	 * Make sure hardware valid bit is not set. We don't do
-	 * tlb flush for this update.
-	 */
-	VM_WARN_ON(pte_hw_valid(*ptep) && !pte_protnone(*ptep));
 
 	/* Note: mm->context.id might not yet have been assigned as
 	 * this context might not have been activated yet when this
-	 * is called.
+	 * is called. Filter the pte value and use the filtered value
+	 * to setup all the ptes in the range.
 	 */
 	pte = set_pte_filter(pte);
 
-	/* Perform the setting of the PTE */
-	arch_enter_lazy_mmu_mode();
+	/*
+	 * We don't need to call arch_enter/leave_lazy_mmu_mode()
+	 * because we expect set_ptes to be only be used on not present
+	 * and not hw_valid ptes. Hence there is no translation cache flush
+	 * involved that need to be batched.
+	 */
 	for (;;) {
+
+		/*
+		 * Make sure hardware valid bit is not set. We don't do
+		 * tlb flush for this update.
+		 */
+		VM_WARN_ON(pte_hw_valid(*ptep) && !pte_protnone(*ptep));
+
+		/* Perform the setting of the PTE */
 		__set_pte_at(mm, addr, ptep, pte, 0);
 		if (--nr == 0)
 			break;
 		ptep++;
-		pte = __pte(pte_val(pte) + (1UL << PTE_RPN_SHIFT));
 		addr += PAGE_SIZE;
+		/*
+		 * increment the pfn.
+		 */
+		pte = pfn_pte(pte_pfn(pte) + 1, pte_pgprot((pte)));
 	}
-	arch_leave_lazy_mmu_mode();
 }
 
 void unmap_kernel_page(unsigned long va)
-- 
2.41.0