From: Michael Ellerman <mpe@ellerman•id.au>
To: Paul Mackerras <paulus@ozlabs•org>, linuxppc-dev@ozlabs•org
Subject: Re: [PATCH 02/11] powerpc: Add Microwatt device tree
Date: Thu, 17 Jun 2021 14:41:28 +1000 [thread overview]
Message-ID: <8735thrtl3.fsf@mpe.ellerman.id.au> (raw)
In-Reply-To: <YMffEN3q5RlLeg4W@thinks.paulus.ozlabs.org>
Paul Mackerras <paulus@ozlabs•org> writes:
>
Little bit of change log never hurts :)
> Signed-off-by: Paul Mackerras <paulus@ozlabs•org>
> ---
> arch/powerpc/boot/dts/microwatt.dts | 105 ++++++++++++++++++++++++++++
> 1 file changed, 105 insertions(+)
> create mode 100644 arch/powerpc/boot/dts/microwatt.dts
>
> diff --git a/arch/powerpc/boot/dts/microwatt.dts b/arch/powerpc/boot/dts/microwatt.dts
> new file mode 100644
> index 000000000000..9b2e64da9432
> --- /dev/null
> +++ b/arch/powerpc/boot/dts/microwatt.dts
> @@ -0,0 +1,105 @@
> +/dts-v1/;
> +
> +/ {
> + #size-cells = <0x02>;
> + #address-cells = <0x02>;
> + model-name = "microwatt";
> + compatible = "microwatt-soc";
> +
> + reserved-memory {
> + #size-cells = <0x02>;
> + #address-cells = <0x02>;
> + ranges;
> + };
> +
> + memory@0 {
> + device_type = "memory";
> + reg = <0x00000000 0x00000000 0x00000000 0x10000000>;
> + };
> +
> + cpus {
> + #size-cells = <0x00>;
> + #address-cells = <0x01>;
> +
> + ibm,powerpc-cpu-features {
> + display-name = "Microwatt";
> + isa = <3000>;
> + device_type = "cpu-features";
> + compatible = "ibm,powerpc-cpu-features";
> +
> + mmu-radix {
> + isa = <3000>;
> + usable-privilege = <2>;
skiboot says 6?
> + os-support = <0x00>;
> + };
> +
> + little-endian {
> + isa = <0>;
I guess you just copied that from skiboot.
The binding says it's required, but AFAICS the kernel doesn't use it.
And isa = 0 mean ISA_BASE, according to the skiboot source.
> + usable-privilege = <3>;
> + os-support = <0x00>;
> + };
> +
> + cache-inhibited-large-page {
> + isa = <0x00>;
> + usable-privilege = <2>;
skiboot says 6, ie. HV and OS.
Don't think it actually matters because you say os-support = 0.
> + os-support = <0x00>;
> + };
> +
> + fixed-point-v3 {
> + isa = <3000>;
> + usable-privilege = <3>;
skiboot says 7.
> + };
> +
> + no-execute {
> + isa = <0x00>;
> + usable-privilege = <2>;
skiboot says 6.
> + os-support = <0x00>;
> + };
> +
> + floating-point {
> + hfscr-bit-nr = <0x00>;
> + hwcap-bit-nr = <0x1b>;
Looks right, bit 27:
#define PPC_FEATURE_HAS_FPU 0x08000000
> + isa = <0x00>;
> + usable-privilege = <0x07>;
> + hv-support = <0x00>;
> + os-support = <0x00>;
> + };
> + };
> +
> + PowerPC,Microwatt@0 {
> + i-cache-sets = <2>;
> + ibm,dec-bits = <64>;
> + reservation-granule-size = <64>;
Never seen that one before.
> + clock-frequency = <100000000>;
> + timebase-frequency = <100000000>;
Those seem quite high?
> + i-tlb-sets = <1>;
> + ibm,ppc-interrupt-server#s = <0>;
> + i-cache-block-size = <64>;
> + d-cache-block-size = <64>;
The kernel reads those, but also hard codes 128 in places.
See L1_CACHE_BYTES.
> + ibm,pa-features = [40 00 c2 27 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00 80 00 80 00 00 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00 80 00];
Do you need that?
You shouldn't, if we've done things right with the cpu-features support.
> + d-cache-sets = <2>;
> + ibm,pir = <0x3c>;
Needed?
> + i-tlb-size = <64>;
> + cpu-version = <0x990000>;
> + status = "okay";
> + i-cache-size = <0x1000>;
> + ibm,processor-radix-AP-encodings = <0x0c 0xa0000010 0x20000015 0x4000001e>;
> + tlb-size = <0>;
> + tlb-sets = <0>;
Does the kernel use those? I can't find it.
> + device_type = "cpu";
> + d-tlb-size = <128>;
> + d-tlb-sets = <2>;
> + reg = <0>;
> + general-purpose;
> + 64-bit;
> + d-cache-size = <0x1000>;
> + ibm,chip-id = <0x00>;
> + };
> + };
> +
> + chosen {
> + bootargs = "";
> + ibm,architecture-vec-5 = [19 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40 00 40];
Do you need that?
I assume you run with MSR[HV] = 1 (you don't say anywhere), in which
case we never look at that property.
cheers
next prev parent reply other threads:[~2021-06-17 4:41 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-14 22:56 [PATCH 00/11] powerpc: Add support for Microwatt soft-core Paul Mackerras
2021-06-14 22:57 ` [PATCH 01/11] powerpc: Add Microwatt platform Paul Mackerras
2021-06-16 18:40 ` Segher Boessenkool
2021-06-16 22:24 ` Paul Mackerras
2021-06-14 22:58 ` [PATCH 02/11] powerpc: Add Microwatt device tree Paul Mackerras
2021-06-17 4:41 ` Michael Ellerman [this message]
2021-06-18 2:58 ` Paul Mackerras
2021-06-14 22:59 ` [PATCH 03/11] powerpc/radix: Add support for microwatt's PRTBL SPR Paul Mackerras
2021-06-15 1:12 ` Nicholas Piggin
2021-06-14 23:00 ` [PATCH 04/11] powerpc/microwatt: Populate platform bus from device-tree Paul Mackerras
2021-06-14 23:00 ` [PATCH 05/11] powerpc/xics: Add a native ICS backend for microwatt Paul Mackerras
2021-06-14 23:01 ` [PATCH 06/11] powerpc: microwatt: Use standard 16550 UART for console Paul Mackerras
2021-06-16 20:42 ` Segher Boessenkool
2021-06-14 23:02 ` [PATCH 07/11] powerpc: Add support for microwatt's hardware random number generator Paul Mackerras
2021-06-15 1:40 ` Nicholas Piggin
2021-06-16 13:16 ` Michael Ellerman
2021-06-16 22:22 ` Paul Mackerras
2021-06-14 23:02 ` [PATCH 08/11] powerpc/microwatt: Add microwatt_defconfig Paul Mackerras
2021-06-14 23:03 ` [PATCH 10/11] powerpc/microwatt: Add a boot wrapper for Microwatt Paul Mackerras
2021-06-14 23:04 ` [PATCH 09/11] powerpc: boot: Fixup device-tree on little endian Paul Mackerras
2021-06-14 23:05 ` [PATCH 11/11] powerpc/microwatt: Disable interrupts in boot wrapper main program Paul Mackerras
2021-06-15 1:21 ` Nicholas Piggin
2021-06-16 23:37 ` Segher Boessenkool
2021-06-17 1:40 ` Nicholas Piggin
2021-06-17 4:06 ` Michael Ellerman
2021-06-17 16:54 ` Segher Boessenkool
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