Subject: Re: [PATCH 1/4] powerpc/mm/radix: Don't iterate all sets when flushing the PWC

From: "Aneesh Kumar K.V" <[email-masked]>
Date: Fri, 14 Jul 2017 11:11:22 +0530

Benjamin Herrenschmidt <[email-masked]> writes:

> The PWC flush only needs a single set call, just like the
> full (RIC=2) flush.
>
> Signed-off-by: Benjamin Herrenschmidt <[email-masked]>
> ---
>  arch/powerpc/mm/tlb-radix.c | 11 +++++++----
>  1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c
> index 02e7140..5403419 100644
> --- a/arch/powerpc/mm/tlb-radix.c
> +++ b/arch/powerpc/mm/tlb-radix.c
> @@ -52,12 +52,15 @@ static inline void _tlbiel_pid(unsigned long pid, unsigned long ric)
>  	 */
>  	__tlbiel_pid(pid, 0, ric);
>
> -	if (ric == RIC_FLUSH_ALL)
> -		/* For the remaining sets, just flush the TLB */
> -		ric = RIC_FLUSH_TLB;
> +	/* For PWC, only one flush is needed */
> +	if (ric == RIC_FLUSH_PWC) {
> +		asm volatile("ptesync": : :"memory");
> +		return;
> +	}
>
> +	/* For the remaining sets, just flush the TLB */
>  	for (set = 1; set < POWER9_TLB_SETS_RADIX ; set++)
> -		__tlbiel_pid(pid, set, ric);
> +		__tlbiel_pid(pid, set, RIC_FLUSH_TLB);
>
>  	asm volatile("ptesync": : :"memory");
>  	asm volatile(PPC_INVALIDATE_ERAT "; isync" : : :"memory");

With the current code, we use tlbiel_pwc() for doing a pwc flush.
and that does what is done this patch. May be we can update this patch
such that we drop tlbiel_pwc and switch all those instance to
tlbiel_pid(pid, RIC_FLUSH_PWC) ?

You already do this in a later patch.

-aneesh