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From: "Aneesh Kumar K.V" <aneesh.kumar@linux•vnet.ibm.com>
To: Paul Mackerras <paulus@samba•org>
Cc: linuxppc-dev@lists•ozlabs.org
Subject: Re: [PATCH -V4 11/12] arch/powerpc: properly offset the context bits for 1T segemnts
Date: Mon, 30 Jul 2012 11:06:27 +0530	[thread overview]
Message-ID: <873949n738.fsf@skywalker.in.ibm.com> (raw)
In-Reply-To: <20120730005803.GB21364@bloggs.ozlabs.ibm.com>

Paul Mackerras <paulus@samba•org> writes:

> On Wed, Jul 25, 2012 at 06:28:04PM +0530, Aneesh Kumar K.V wrote:
>> From: "Aneesh Kumar K.V" <aneesh.kumar@linux•vnet.ibm.com>
>> 
>> We should do rldimi r10,r9,USER_ESID_BITS,0 only after populating
>> r10 with ESID bits.
>
> This needs a lot more explanation as to what the problem is that this
> patch aims to fix.  Is it a problem today without your other patches,
> or is it introduced by previous patches?
>
> In any case I think there is an error in the patch, see below...
>
>>  0:	/* user address: proto-VSID = context << 15 | ESID. First check
>> @@ -155,13 +157,16 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
>>  	ld	r9,PACACONTEXTID(r13)
>>  BEGIN_FTR_SECTION
>>  	cmpldi	r10,0x1000
>> +	bge	9f
>>  END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
>>  	rldimi	r10,r9,USER_ESID_BITS,0
>> +	b	slb_finish_load
>>  BEGIN_FTR_SECTION
>> -	bge	slb_finish_load_1T
>> +9:
>> +	srdi	r10,r10,40-28		/* get 1T ESID */
>> +	rldimi	r10,r9,USER_ESID_BITS,0
>
> Shouldn't this one be USER_ESID_BITS_1T?  And in that case, since
> USER_ESID_BITS == USER_ESID_BITS_1T + 12, I think the patch would
> then introduce no change in behaviour (other than being slightly
> slower than the current code).  Or am I missing something? -- in
> that case we really need a longer and better explanation with the
> patch.

Ok I missed that we used USER_ESID_BITS there. This patch can be
dropped. I looked at the 1T code, and assumed that we were wrongly
shifting the context bits there.

-aneesh

  reply	other threads:[~2012-07-30  5:37 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-07-25 12:57 [PATCH -V4 0/12] arch/powerpc: Add 64TB support to ppc64 Aneesh Kumar K.V
2012-07-25 12:57 ` [PATCH -V4 01/12] arch/powerpc: Use hpt_va to compute virtual address Aneesh Kumar K.V
2012-07-25 12:57 ` [PATCH -V4 02/12] arch/powerpc: Simplify hpte_decode Aneesh Kumar K.V
2012-07-25 12:57 ` [PATCH -V4 03/12] arch/powerpc: Convert virtual address to vpn Aneesh Kumar K.V
2012-07-25 12:57 ` [PATCH -V4 04/12] arch/powerpc: Rename va " Aneesh Kumar K.V
2012-07-25 12:57 ` [PATCH -V4 05/12] arch/powerpc: Make KERN_VIRT_SIZE not dependend on PGTABLE_RANGE Aneesh Kumar K.V
2012-07-25 12:57 ` [PATCH -V4 06/12] arch/powerpc: Increase the slice range to 64TB Aneesh Kumar K.V
2012-07-25 12:58 ` [PATCH -V4 07/12] arch/powerpc: Make some of the PGTABLE_RANGE dependency explicit Aneesh Kumar K.V
2012-07-25 12:58 ` [PATCH -V4 08/12] arch/powerpc: Use the rquired number of VSID bits in slbmte Aneesh Kumar K.V
2012-07-25 12:58 ` [PATCH -V4 09/12] arch/powerpc: Use 32bit array for slb cache Aneesh Kumar K.V
2012-07-25 12:58 ` [PATCH -V4 10/12] arch/powerpc: Add 64TB support Aneesh Kumar K.V
2012-07-25 12:58 ` [PATCH -V4 11/12] arch/powerpc: properly offset the context bits for 1T segemnts Aneesh Kumar K.V
2012-07-30  0:58   ` Paul Mackerras
2012-07-30  5:36     ` Aneesh Kumar K.V [this message]
2012-07-25 12:58 ` [PATCH -V4 12/12] arch/powerpc: properly isolate kernel and user proto-VSID Aneesh Kumar K.V
2012-07-25 15:21   ` Aneesh Kumar K.V

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