From: Michael Ellerman <mpe@ellerman•id.au>
To: Joel Stanley <joel@jms•id.au>
Cc: linuxppc-dev@lists•ozlabs.org, Nicholas Piggin <npiggin@gmail•com>
Subject: Re: [PATCH 4/4] powerpc/64s: Use POWER10 stsync barrier for wmb()
Date: Fri, 25 Aug 2023 16:59:23 +1000 [thread overview]
Message-ID: <877cpjvc8k.fsf@mail.lhotse> (raw)
In-Reply-To: <CACPK8Xeq3G2g2nY1_Wm32tB0JyfS5k+=YAjQNom3x=cc2Qs7mA@mail.gmail.com>
Joel Stanley <joel@jms•id.au> writes:
> On Thu, 24 Aug 2023 at 12:12, Michael Ellerman <mpe@ellerman•id.au> wrote:
>>
>> Michael Ellerman <mpe@ellerman•id.au> writes:
>> > Michael Ellerman <mpe@ellerman•id.au> writes:
>> >> "Nicholas Piggin" <npiggin@gmail•com> writes:
>> >>> On Wed Jun 14, 2023 at 3:56 PM AEST, Michael Ellerman wrote:
>> >>>> Michael Ellerman <mpe@ellerman•id.au> writes:
>> >>>> > Nicholas Piggin <npiggin@gmail•com> writes:
>> >>>> >> The most expensive ordering for hwsync to provide is the store-load
>> >>>> >> barrier, because all prior stores have to be drained to the caches
>> >>>> >> before subsequent instructions can complete.
>> >>>> >>
>> >>>> >> stsync just orders stores which means it can just be a barrer that
>> >>>> >> goes down the store queue and orders draining, and does not prevent
>> >>>> >> completion of subsequent instructions. So it should be faster than
>> >>>> >> hwsync.
>> >>>> >>
>> >>>> >> Use stsync for wmb(). Older processors that don't recognise the SC
>> >>>> >> field should treat this as hwsync.
>> >>>> >
>> >>>> > qemu (7.1) emulating ppc64e does not :/
>> >>>> >
>> >>>> > mpic: Setting up MPIC " OpenPIC " version 1.2 at fe0040000, max 1 CPUs
>> >>>> > mpic: ISU size: 256, shift: 8, mask: ff
>> >>>> > mpic: Initializing for 256 sources
>> >>>> > Oops: Exception in kernel mode, sig: 4 [#1]
>> >>>> ..
>> >>>> >
>> >>>> > I guess just put it behind an #ifdef 64S.
>> >>>>
>> >>>> That doesn't work because qemu emulating a G5 also doesn't accept it.
>> >>>>
>> >>>> So either we need to get qemu updated and wait a while for that to
>> >>>> percolate, or do some runtime patching of wmbs in the kernel >_<
>> >>>
>> >>> Gah, sorry. QEMU really should be ignoring reserved fields in
>> >>> instructions :(
>> >>
>> >> Yeah, it's an annoying discrepancy vs real hardware and the ISA.
>> >>
>> >>> I guess leave it out for now. Should fix QEMU but we probably also need
>> >>> to do patching so as not to break older QEMUs.
>> >>
>> >> I'll plan to take the first 3 patches, they seem OK as-is.
>> >
>> > I didn't do that in the end, because patch 2 suffers from the same
>> ^
>> 3
>> > problem of not working on QEMU.
>
> Did we get a patch to fix this in to Qemu?
No. Nick might have looked at it but he hasn't posted anything AFAIK.
cheers
prev parent reply other threads:[~2023-08-25 7:00 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-09 10:00 [PATCH 1/4] powerpc: Make mmiowb a wmb Nicholas Piggin
2023-06-09 10:00 ` [PATCH 2/4] powerpc/64s: Add POWER10 store sync mnemonics Nicholas Piggin
2023-06-13 5:31 ` Joel Stanley
2023-06-14 5:31 ` Nicholas Piggin
2023-06-09 10:00 ` [PATCH 3/4] powerpc/64s: Use stncisync instruction for smp_wmb() when available Nicholas Piggin
2023-06-09 10:00 ` [PATCH 4/4] powerpc/64s: Use POWER10 stsync barrier for wmb() Nicholas Piggin
2023-06-13 13:59 ` Michael Ellerman
2023-06-14 5:56 ` Michael Ellerman
2023-06-15 1:53 ` Nicholas Piggin
2023-06-15 3:09 ` Michael Ellerman
2023-08-24 12:11 ` Michael Ellerman
2023-08-24 12:12 ` Michael Ellerman
2023-08-25 0:28 ` Joel Stanley
2023-08-25 6:59 ` Michael Ellerman [this message]
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