From: Michael Ellerman <mpe@ellerman•id.au>
To: Jordan Niethe <jniethe5@gmail•com>, linuxppc-dev@lists•ozlabs.org
Cc: Jordan Niethe <jniethe5@gmail•com>
Subject: Re: [PATCH v2] powerpc: Update documentation of ISA versions for Power10
Date: Thu, 27 Aug 2020 16:18:31 +1000 [thread overview]
Message-ID: <87ft88393c.fsf@mpe.ellerman.id.au> (raw)
In-Reply-To: <20200827040556.1783-1-jniethe5@gmail.com>
Jordan Niethe <jniethe5@gmail•com> writes:
> Update the CPU to ISA Version Mapping document to include Power10 and
> ISA v3.1.
>
> Signed-off-by: Jordan Niethe <jniethe5@gmail•com>
> ---
> v2: Transactional Memory = No
> ---
> Documentation/powerpc/isa-versions.rst | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/powerpc/isa-versions.rst b/Documentation/powerpc/isa-versions.rst
> index a363d8c1603c..3873bbba183a 100644
> --- a/Documentation/powerpc/isa-versions.rst
> +++ b/Documentation/powerpc/isa-versions.rst
> @@ -62,6 +65,7 @@ PPC970 No
> ========== ====================================
> CPU Transactional Memory
> ========== ====================================
> +Power10 No (* see Power ISA v3.1 Appendix A.)
There's three "Appendix A"s in ISA v3.1.
There's one in Book I, and one in Book II.
And then the one you're referring to is not actually in Book III, it's
listed after Book III, and is apparently an appendix to all three books?
Which is just utterly confusing.
So I'll change it to say:
"Appendix A. Notes on the Removal of Transactional Memory from the Architecture"
Which is very long, but at least you can search for it.
cheers
next prev parent reply other threads:[~2020-08-27 6:20 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-27 4:05 [PATCH v2] powerpc: Update documentation of ISA versions for Power10 Jordan Niethe
2020-08-27 4:49 ` Christophe Leroy
2020-08-27 5:00 ` Jordan Niethe
2020-08-27 6:18 ` Michael Ellerman [this message]
2020-09-09 13:27 ` Michael Ellerman
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