From: Michael Ellerman <mpe@ellerman•id.au>
To: Athira Rajeev <atrajeev@linux•vnet.ibm.com>,
Jordan Niethe <jniethe5@gmail•com>
Cc: Gautham R Shenoy <ego@linux•vnet.ibm.com>,
Michael Neuling <mikey@neuling•org>,
maddy@linux•vnet.ibm.com, kvm@vger•kernel.org,
kvm-ppc@vger•kernel.org, svaidyan@in•ibm.com, acme@kernel•org,
jolsa@kernel•org, linuxppc-dev <linuxppc-dev@lists•ozlabs.org>
Subject: Re: [v3 07/15] powerpc/perf: Add power10_feat to dt_cpu_ftrs
Date: Wed, 22 Jul 2020 20:39:00 +1000 [thread overview]
Message-ID: <87ft9jrfzv.fsf@mpe.ellerman.id.au> (raw)
In-Reply-To: <9A4E06A2-5686-4C85-B2F7-0904F195B58A@linux.vnet.ibm.com>
Athira Rajeev <atrajeev@linux•vnet.ibm.com> writes:
>> On 22-Jul-2020, at 10:11 AM, Jordan Niethe <jniethe5@gmail•com> wrote:
>>
>> On Sat, Jul 18, 2020 at 1:13 AM Athira Rajeev
>> <atrajeev@linux•vnet.ibm.com <mailto:atrajeev@linux•vnet.ibm.com>> wrote:
>>>
>>> From: Madhavan Srinivasan <maddy@linux•ibm.com>
>>>
>>> Add power10 feature function to dt_cpu_ftrs.c along
>>> with a power10 specific init() to initialize pmu sprs,
>>> sets the oprofile_cpu_type and cpu_features. This will
>>> enable performance monitoring unit(PMU) for Power10
>>> in CPU features with "performance-monitor-power10".
>>>
>>> For PowerISA v3.1, BHRB disable is controlled via Monitor Mode
>>> Control Register A (MMCRA) bit, namely "BHRB Recording Disable
>>> (BHRBRD)". This patch initializes MMCRA BHRBRD to disable BHRB
>>> feature at boot for power10.
>>>
>>> Signed-off-by: Madhavan Srinivasan <maddy@linux•ibm.com>
>>> ---
>>> arch/powerpc/include/asm/reg.h | 3 +++
>>> arch/powerpc/kernel/cpu_setup_power.S | 8 ++++++++
>>> arch/powerpc/kernel/dt_cpu_ftrs.c | 26 ++++++++++++++++++++++++++
>>> 3 files changed, 37 insertions(+)
>>>
>>> diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
>>> index 21a1b2d..900ada1 100644
>>> --- a/arch/powerpc/include/asm/reg.h
>>> +++ b/arch/powerpc/include/asm/reg.h
>>> @@ -1068,6 +1068,9 @@
>>> #define MMCR0_PMC2_LOADMISSTIME 0x5
>>> #endif
>>>
>>> +/* BHRB disable bit for PowerISA v3.10 */
>>> +#define MMCRA_BHRB_DISABLE 0x0000002000000000
>> Shouldn't this go under SPRN_MMCRA with the other MMCRA_*.
>
>
> Hi Jordan
>
> Ok, the definition of MMCRA is under #ifdef for 64 bit . if I move definition of MMCRA_BHRB_DISABLE along with other SPR's, I also
> need to define this for 32-bit to satisfy core-book3s to compile as below:
>
> diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
> index 900ada10762c..7e271657b412 100644
> --- a/arch/powerpc/include/asm/reg.h
> +++ b/arch/powerpc/include/asm/reg.h
> @@ -888,6 +888,8 @@
> #define MMCRA_SLOT 0x07000000UL /* SLOT bits (37-39) */
> #define MMCRA_SLOT_SHIFT 24
> #define MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
> +/* BHRB disable bit for PowerISA v3.10 */
> +#define MMCRA_BHRB_DISABLE 0x0000002000000000
I changed it to:
#define MMCRA_BHRB_DISABLE 0x2000000000UL // BHRB disable bit for ISA v3.1
>>> diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
>>> index efdcfa7..b8e0d1e 100644
>>> --- a/arch/powerpc/kernel/cpu_setup_power.S
>>> +++ b/arch/powerpc/kernel/cpu_setup_power.S
>>> @@ -94,6 +94,7 @@ _GLOBAL(__restore_cpu_power8)
>>> _GLOBAL(__setup_cpu_power10)
>>> mflr r11
>>> bl __init_FSCR_power10
>>> + bl __init_PMU_ISA31
>> So we set MMCRA here but then aren't we still going to call __init_PMU
>> which will overwrite that?
>> Would this setting MMCRA also need to be handled in __restore_cpu_power10?
>
> Thanks for this nice catch ! When I rebased code initial phase, we didn’t had power10 part filled in.
> It was a miss from my side in adding PMu init functions and thanks for pointing this out.
> Below patch will call __init_PMU functions in setup and restore. Please check if this looks good
Actually those changes should be in a separate patch.
This one is wiring up DT CPU features, the cpu setup routines are not
used by DT CPU features.
So please send a new patch I can insert into the series that adds the
cpu_setup_power.S changes.
cheers
> --
> diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
> index efdcfa714106..e672a6c5fd7c 100644
> --- a/arch/powerpc/kernel/cpu_setup_power.S
> +++ b/arch/powerpc/kernel/cpu_setup_power.S
> @@ -94,6 +94,9 @@ _GLOBAL(__restore_cpu_power8)
> _GLOBAL(__setup_cpu_power10)
> mflr r11
> bl __init_FSCR_power10
> + bl __init_PMU
> + bl __init_PMU_ISA31
> + bl __init_PMU_HV
> b 1f
>
> _GLOBAL(__setup_cpu_power9)
> @@ -124,6 +127,9 @@ _GLOBAL(__setup_cpu_power9)
> _GLOBAL(__restore_cpu_power10)
> mflr r11
> bl __init_FSCR_power10
> + bl __init_PMU
> + bl __init_PMU_ISA31
> + bl __init_PMU_HV
> b 1f
>
> _GLOBAL(__restore_cpu_power9)
> @@ -233,3 +239,10 @@ __init_PMU_ISA207:
> li r5,0
> mtspr SPRN_MMCRS,r5
> blr
> +
> +__init_PMU_ISA31:
> + li r5,0
> + mtspr SPRN_MMCR3,r5
> + LOAD_REG_IMMEDIATE(r5, MMCRA_BHRB_DISABLE)
> + mtspr SPRN_MMCRA,r5
> + blr
>
next prev parent reply other threads:[~2020-07-22 10:40 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-17 14:38 [v3 00/15] powerpc/perf: Add support for power10 PMU Hardware Athira Rajeev
2020-07-17 14:38 ` [v3 01/15] powerpc/perf: Update cpu_hw_event to use `struct` for storing MMCR registers Athira Rajeev
2020-07-21 3:42 ` Jordan Niethe
2020-07-22 2:15 ` Athira Rajeev
2020-07-17 14:38 ` [v3 02/15] KVM: PPC: Book3S HV: Cleanup updates for kvm vcpu MMCR Athira Rajeev
2020-07-21 3:54 ` Paul Mackerras
2020-07-22 2:09 ` Athira Rajeev
2020-07-22 4:37 ` Michael Ellerman
2020-07-22 5:49 ` Athira Rajeev
2020-07-22 4:54 ` Paul Mackerras
2020-07-22 6:03 ` Madhavan Srinivasan
2020-07-22 4:38 ` Michael Ellerman
2020-07-17 14:38 ` [v3 03/15] powerpc/perf: Update Power PMU cache_events to u64 type Athira Rajeev
2020-07-17 14:38 ` [v3 04/15] powerpc/perf: Add support for ISA3.1 PMU SPRs Athira Rajeev
2020-07-22 4:18 ` Jordan Niethe
2020-07-22 8:07 ` Athira Rajeev
2020-07-22 10:52 ` Jordan Niethe
2020-07-22 12:03 ` Michael Ellerman
2020-07-17 14:38 ` [v3 05/15] KVM: PPC: Book3S HV: Save/restore new PMU registers Athira Rajeev
2020-07-17 14:38 ` [v3 06/15] powerpc/xmon: Add PowerISA v3.1 PMU SPRs Athira Rajeev
2020-07-17 14:38 ` [v3 07/15] powerpc/perf: Add power10_feat to dt_cpu_ftrs Athira Rajeev
2020-07-22 4:41 ` Jordan Niethe
2020-07-22 7:55 ` Athira Rajeev
2020-07-22 10:39 ` Michael Ellerman [this message]
2020-07-22 10:49 ` Jordan Niethe
2020-07-22 12:28 ` Athira Rajeev
2020-07-17 14:38 ` [v3 08/15] powerpc/perf: power10 Performance Monitoring support Athira Rajeev
2020-07-17 14:38 ` [v3 09/15] powerpc/perf: Ignore the BHRB kernel address filtering for P10 Athira Rajeev
2020-07-17 14:38 ` [v3 10/15] powerpc/perf: Add Power10 BHRB filter support for PERF_SAMPLE_BRANCH_IND_CALL/COND Athira Rajeev
2020-07-17 14:38 ` [v3 11/15] powerpc/perf: BHRB control to disable BHRB logic when not used Athira Rajeev
2020-07-20 10:05 ` Gautham R Shenoy
2020-07-23 1:26 ` Jordan Niethe
2020-07-23 1:28 ` Jordan Niethe
2020-07-17 14:38 ` [v3 12/15] powerpc/perf: Add support for outputting extended regs in perf intr_regs Athira Rajeev
2020-07-19 11:17 ` kernel test robot
2020-07-20 8:09 ` Athira Rajeev
2020-07-21 6:02 ` kajoljain
2020-07-23 5:44 ` kajoljain
2020-07-23 14:56 ` Arnaldo Carvalho de Melo
2020-07-24 8:25 ` Athira Rajeev
2020-07-24 12:26 ` Ravi Bangoria
2020-07-24 18:13 ` Athira Rajeev
2020-07-17 14:38 ` [v3 13/15] tools/perf: Add perf tools support for extended register capability in powerpc Athira Rajeev
2020-07-21 6:03 ` kajoljain
2020-07-24 11:02 ` Ravi Bangoria
2020-07-24 18:02 ` Athira Rajeev
2020-07-17 14:38 ` [v3 14/15] powerpc/perf: Add extended regs support for power10 platform Athira Rajeev
2020-07-21 6:03 ` kajoljain
2020-07-17 14:38 ` [v3 15/15] tools/perf: Add perf tools support for extended regs in power10 Athira Rajeev
2020-07-21 6:04 ` kajoljain
2020-07-24 13:24 ` [v3 00/15] powerpc/perf: Add support for power10 PMU Hardware Michael Ellerman
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