Subject: Re: [PATCH 02/13] powerpc/64: Provide functions for accessing POWER9 partition table

From: "Aneesh Kumar K.V" <[email-masked]>
Date: Sat, 19 Nov 2016 12:05:21 +0530

Paul Mackerras <[email-masked]> writes:

> On Fri, Nov 18, 2016 at 07:57:30PM +0530, Aneesh Kumar K.V wrote:
>> Paul Mackerras <[email-masked]> writes:
>>  +
>> > +	/* Global flush of TLBs and partition table caches for this lpid */
>> > +	asm volatile("ptesync");
>> > +	asm volatile(PPC_TLBIE_5(%0,%1,2,0,0) : : "r"(0x800), "r" (lpid));
>> > +	asm volatile("eieio; tlbsync; ptesync" : : : "memory");
>> > +}
>> 
>> 
>> It would be nice to convert that 0x800 to a documented IS value or better use
>> radix__flush_tlb_pid() ?
>
> Well, not radix__flush_tlb_pid - this isn't radix and it isn't a PID
> flush.  I could use TLBIEL_INVAL_SET_LPID except the name implies it's
> for tlbiel and this is a tlbie.
>

I wrote that wrong, we really don't have tlb_pid() what we have is tlb_lpid().

void radix__flush_tlb_lpid(unsigned long lpid)
{
	unsigned long rb,rs,prs,r;
	unsigned long ric = RIC_FLUSH_ALL;

	rb = 0x2 << PPC_BITLSHIFT(53); /* IS = 2 */
	rs = lpid & ((1UL << 32) - 1);
	prs = 0; /* partition scoped */
	r = 1;   /* raidx format */

	asm volatile("ptesync": : :"memory");
	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
	asm volatile("eieio; tlbsync; ptesync": : :"memory");
}