Subject: Re: [RFC][PATCH] powerpc/64s: Leave IRQs hard enabled over context switch

From: Michael Ellerman <[email-masked]>
Date: Wed, 03 May 2017 20:26:59 +1000

Benjamin Herrenschmidt <[email-masked]> writes:

> On Wed, 2017-05-03 at 17:34 +1000, Nicholas Piggin wrote:
>> Extending the soft IRQ disable to cover PMU interrupts will allow this
>> hard disable to be removed from hash based kernels too, but they will
>> still have to soft-disable PMU interrupts.
>> 
>> - Q1: Can we do this? It gives nice profiles of context switch code
>>   rather than assigning it all to local_irq_enable.
>
> Probably ok with radix yes.
>
>> - Q2: What is the unrecoverable SLB miss on exception entry? Is there
>>   anywhere we access the kernel stack with RI disabled? Something else?
>
> Not sure what you mean by Q2, but the original problem is an occurrence
> of what we call the 'megabug' which hit us in different forms over the
> years, and happens when we get a kernel stack SLB entry wrong.
>
> Normally, the segment containing the current kernel stack is always
> bolted in the SLB in a specific slot. If we accidentally lose that
> "bolt", we can end up faulting it into the wrong slot, thus making it
> possible for it to get evicted later on etc...
>
> That in turns hits the exception return path which accesses the kernel
> stack after clearing RI and setting SRR0/1 to the return values.

Couldn't we avoid the whole problem by just having two bolted slots for
the stack, meaning we could have the current and next stack bolted at
all times.

That would mean we'd be using 4 slots for bolted entries, which is one
more than 3 - but it might be a good trade off.

Or we could make the SLB insertion algorithm smarter so that we could
later free the slot that was used for previous kernel stack.

cheers