Subject: Re: [PATCH] Xilinx UART Lite 2.6.18 driver

From: Peter Korsgaard <[email-masked]>
Date: Fri, 20 Oct 2006 21:41:34 +0200

>>>>> "David" == David Bolcsfoldi <[email-masked]> writes:

Hi - sorry for the slow response, this week has been crazy :/

>> Could you make it relative to my driver so the changes are easier
>> to see?

David> Done and done. Look at the end of this e-mail.

Thanks.

>> The PPC is big endian - Did you remember to add 3 to your base
>> address?

David> I don't see how reading a single byte would be affected by the
David> endianess of the platform.  I think it has more to do with the
David> fact that the status and control registers are both 4 byte wide
David> and when you add 3 to your offset you read only the LSB. I also
David> suspect that the RX and TX registers are 4 byte wide too, even
David> though this is not stated explicitly in the documentation I
David> think it would be prudent to access these two as 4-byte wide
David> registers as well.

Well, the end result is the same. I guess the only reason for the
4-byte spacing between the registers is the 32bit width of the OPB
bus. The logical contents of the registers are all 8bit or less, and
sticking to 8bit access makes things easier (no endianness issues, no
issues with alternative implementations with another physical width).

E.G. the driver might be useful for other architectures
(E.G. microblaze) and for other implementations of the uartlite. We
are using another uart with a uartlite compatible interface in a
non-virtex fpga.

The exact same thing is done my 8250.c for the 16550 opb core.

David> I guess it is OK to read and write bytes as long as the
David> bitflags don't change location. But I believe it is stated in
David> the documentation that the OPB UART Lite device is a big endian
David> device, in my opinion it would better to honor this and do big
David> endian access of register width.

The driver has to be updated If the hardware interface changes no
matter what. The documentation clearly states (bottom of page 3) that
you can access the registers using 8, 16 or 32bit accesses.

I'll test and take a closer look at your patch when I have access to
hw again on Monday.

-- 
Bye, Peter Korsgaard