* [PATCH 0/4] Misc patches for the 2.6.24 merge window
@ 2007-10-23 4:27 Grant Likely
2007-10-23 4:27 ` [PATCH 1/4] bootwrapper: Allow wrapper script to execute verbosely Grant Likely
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Grant Likely @ 2007-10-23 4:27 UTC (permalink / raw)
To: paulus, linuxppc-dev; +Cc: David Gibson
Paulus,
Here is the last set of patches that I'd like to get in before Linus
slams the merge window shut. They're pretty minor changes. The wrapper
patches make it easier to debug and catch errors and David has already
okayed them. There's a speedup on the uartlite driver, and then a chunk
of documentation for the Xilinx device tree bindings.
Josh, can you please ack or nack the documentation change?
Peter, any issues with the uartlite change?
Cheers,
g.
--
Grant Likely, B.Sc. P.Eng.
Secret Lab Technologies Ltd.
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 1/4] bootwrapper: Allow wrapper script to execute verbosely 2007-10-23 4:27 [PATCH 0/4] Misc patches for the 2.6.24 merge window Grant Likely @ 2007-10-23 4:27 ` Grant Likely 2007-10-23 4:27 ` [PATCH 2/4] bootwrapper: Bail from script if any command fails Grant Likely ` (2 subsequent siblings) 3 siblings, 0 replies; 7+ messages in thread From: Grant Likely @ 2007-10-23 4:27 UTC (permalink / raw) To: paulus, linuxppc-dev; +Cc: David Gibson From: Grant Likely <grant.likely@secretlab•ca> Allow wrapper script to print verbose progress when the V is set in the environment. Signed-off-by: Grant Likely <grant.likely@secretlab•ca> Acked-by: David Gibson <david@gibson•dropbear.id.au> --- arch/powerpc/boot/wrapper | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper index 39b27e5..347639c 100755 --- a/arch/powerpc/boot/wrapper +++ b/arch/powerpc/boot/wrapper @@ -21,6 +21,11 @@ # (default ./arch/powerpc/boot) # -W dir specify working directory for temporary files (default .) +# Allow for verbose output +if [ "$V" = 1 ]; then + set -x +fi + # defaults kernel= ofile=zImage ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/4] bootwrapper: Bail from script if any command fails 2007-10-23 4:27 [PATCH 0/4] Misc patches for the 2.6.24 merge window Grant Likely 2007-10-23 4:27 ` [PATCH 1/4] bootwrapper: Allow wrapper script to execute verbosely Grant Likely @ 2007-10-23 4:27 ` Grant Likely 2007-10-23 4:27 ` [PATCH 3/4] Device tree bindings for Xilinx devices Grant Likely 2007-10-23 4:27 ` [PATCH 4/4] Uartlite: speed up console output Grant Likely 3 siblings, 0 replies; 7+ messages in thread From: Grant Likely @ 2007-10-23 4:27 UTC (permalink / raw) To: paulus, linuxppc-dev; +Cc: David Gibson From: Grant Likely <grant.likely@secretlab•ca> Add the 'set -e' command to the wrapper script so that if any command fails then the script will automatically exit Signed-off-by: Grant Likely <grant.likely@secretlab•ca> Acked-by: David Gibson <david@gibson•dropbear.id.au> --- arch/powerpc/boot/wrapper | 27 ++++++++++----------------- 1 files changed, 10 insertions(+), 17 deletions(-) diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper index 347639c..5ae48f4 100755 --- a/arch/powerpc/boot/wrapper +++ b/arch/powerpc/boot/wrapper @@ -21,6 +21,9 @@ # (default ./arch/powerpc/boot) # -W dir specify working directory for temporary files (default .) +# Stop execution if any command fails +set -e + # Allow for verbose output if [ "$V" = 1 ]; then set -x @@ -116,7 +119,7 @@ if [ -n "$dts" ]; then if [ -z "$dtb" ]; then dtb="$platform.dtb" fi - dtc -O dtb -o "$dtb" -b 0 -V 16 "$dts" || exit 1 + dtc -O dtb -o "$dtb" -b 0 -V 16 "$dts" fi if [ -z "$kernel" ]; then @@ -287,23 +290,13 @@ ps3) rm -f "$object/otheros.bld" - msg=$(dd if="$ofile.bin" of="$ofile.bin" conv=notrunc \ - skip=$overlay_dest seek=$system_reset_kernel \ - count=$overlay_size bs=1 2>&1) - - if [ $? -ne "0" ]; then - echo $msg - exit 1 - fi + dd if="$ofile.bin" of="$ofile.bin" conv=notrunc \ + skip=$overlay_dest seek=$system_reset_kernel \ + count=$overlay_size bs=1 - msg=$(dd if="$ofile.bin" of="$ofile.bin" conv=notrunc \ - skip=$system_reset_overlay seek=$overlay_dest \ - count=$overlay_size bs=1 2>&1) - - if [ $? -ne "0" ]; then - echo $msg - exit 2 - fi + dd if="$ofile.bin" of="$ofile.bin" conv=notrunc \ + skip=$system_reset_overlay seek=$overlay_dest \ + count=$overlay_size bs=1 gzip --force -9 --stdout "$ofile.bin" > "$object/otheros.bld" ;; ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/4] Device tree bindings for Xilinx devices 2007-10-23 4:27 [PATCH 0/4] Misc patches for the 2.6.24 merge window Grant Likely 2007-10-23 4:27 ` [PATCH 1/4] bootwrapper: Allow wrapper script to execute verbosely Grant Likely 2007-10-23 4:27 ` [PATCH 2/4] bootwrapper: Bail from script if any command fails Grant Likely @ 2007-10-23 4:27 ` Grant Likely 2007-10-23 12:36 ` Josh Boyer 2007-10-23 4:27 ` [PATCH 4/4] Uartlite: speed up console output Grant Likely 3 siblings, 1 reply; 7+ messages in thread From: Grant Likely @ 2007-10-23 4:27 UTC (permalink / raw) To: paulus, linuxppc-dev; +Cc: David Gibson From: Grant Likely <grant.likely@secretlab•ca> Signed-off-by: Grant Likely <grant.likely@secretlab•ca> Acked-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx•com> --- Documentation/powerpc/booting-without-of.txt | 261 ++++++++++++++++++++++++++ 1 files changed, 261 insertions(+), 0 deletions(-) diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt index a96e853..59df69d 100644 --- a/Documentation/powerpc/booting-without-of.txt +++ b/Documentation/powerpc/booting-without-of.txt @@ -52,6 +52,7 @@ Table of Contents i) Freescale QUICC Engine module (QE) j) CFI or JEDEC memory-mapped NOR flash k) Global Utilities Block + l) Xilinx IP cores VII - Specifying interrupt information for devices 1) interrupts property @@ -2242,6 +2243,266 @@ platforms are moved over to use the flattened-device-tree model. available. For Axon: 0x0000012a + l) Xilinx IP cores + + The Xilinx EDK toolchain ships with a set of IP cores (devices) for use + in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range + of standard device types (network, serial, etc.) and miscellanious + devices (gpio, LCD, spi, etc). Also, since these devices are + implemented within the fpga fabric every instance of the device can be + synthesised with different options that change the behaviour. + + Each IP-core has a set of parameters which the FPGA designer can use to + control how the core is synthesized. Historically, the EDK tool would + extract the device parameters relevant to device drivers and copy them + into an 'xparameters.h' in the form of #define symbols. This tells the + device drivers how the IP cores are configured, but it requres the kernel + to be recompiled every time the FPGA bitstream is resynthesized. + + The new approach is to export the parameters into the device tree and + generate a new device tree each time the FPGA bitstream changes. The + parameters which used to be exported as #defines will now become + properties of the device node. In general, device nodes for IP-cores + will take the following form: + + (name)@(base-address) { + compatible = "xlnx,(ip-core-name)-(HW_VER)" + [, (list of compatible devices), ...]; + reg = <(baseaddr) (size)>; + interrupt-parent = <&interrupt-controller-phandle>; + interrupts = < ... >; + xlnx,(parameter1) = "(string-value)"; + xlnx,(parameter2) = <(int-value)>; + }; + + (ip-core-name): the name of the ip block (given after the BEGIN + directive in system.mhs). Should be in lowercase + and all underscores '_' converted to dashes '-'. + (name): is derived from the "PARAMETER INSTANCE" value. + (parameter#): C_* parameters from system.mhs. The C_ prefix is + dropped from the parameter name, the name is converted + to lowercase and all underscore '_' characters are + converted to dashes '-'. + (baseaddr): the C_BASEADDR parameter. + (HW_VER): from the HW_VER parameter. + (size): equals C_HIGHADDR - C_BASEADDR + 1 + + Typically, the compatible list will include the exact IP core version + followed by an older IP core version which implements the same + interface or any other device with the same interface. + + 'reg', 'interrupt-parent' and 'interrupts' are all optional properties. + + For example, the following block from system.mhs: + + BEGIN opb_uartlite + PARAMETER INSTANCE = opb_uartlite_0 + PARAMETER HW_VER = 1.00.b + PARAMETER C_BAUDRATE = 115200 + PARAMETER C_DATA_BITS = 8 + PARAMETER C_ODD_PARITY = 0 + PARAMETER C_USE_PARITY = 0 + PARAMETER C_CLK_FREQ = 50000000 + PARAMETER C_BASEADDR = 0xEC100000 + PARAMETER C_HIGHADDR = 0xEC10FFFF + BUS_INTERFACE SOPB = opb_7 + PORT OPB_Clk = CLK_50MHz + PORT Interrupt = opb_uartlite_0_Interrupt + PORT RX = opb_uartlite_0_RX + PORT TX = opb_uartlite_0_TX + PORT OPB_Rst = sys_bus_reset_0 + END + + becomes the following device tree node: + + opb-uartlite-0@ec100000 { + device_type = "serial"; + compatible = "xlnx,opb-uartlite-1.00.b"; + reg = <ec100000 10000>; + interrupt-parent = <&opb-intc>; + interrupts = <1 0>; // got this from the opb_intc parameters + current-speed = <d#115200>; // standard serial device prop + clock-frequency = <d#50000000>; // standard serial device prop + xlnx,data-bits = <8>; + xlnx,odd-parity = <0>; + xlnx,use-parity = <0>; + }; + + Some IP cores actually implement 2 or more logical devices. In this case, + the device should still describe the whole IP core with a single node + and add a child node for each logical device. The ranges property can + be used to translate from parent IP-core to the registers of each device. + (Note: this makes the assumption that both logical devices have the same + bus binding. If this is not true, then separate nodes should be used for + each logical device). The 'cell-index' property can be used to enumerate + logical devices within an IP core. For example, the following is the + system.mhs entry for the dual ps2 controller found on the ml403 reference + design. + + BEGIN opb_ps2_dual_ref + PARAMETER INSTANCE = opb_ps2_dual_ref_0 + PARAMETER HW_VER = 1.00.a + PARAMETER C_BASEADDR = 0xA9000000 + PARAMETER C_HIGHADDR = 0xA9001FFF + BUS_INTERFACE SOPB = opb_v20_0 + PORT Sys_Intr1 = ps2_1_intr + PORT Sys_Intr2 = ps2_2_intr + PORT Clkin1 = ps2_clk_rx_1 + PORT Clkin2 = ps2_clk_rx_2 + PORT Clkpd1 = ps2_clk_tx_1 + PORT Clkpd2 = ps2_clk_tx_2 + PORT Rx1 = ps2_d_rx_1 + PORT Rx2 = ps2_d_rx_2 + PORT Txpd1 = ps2_d_tx_1 + PORT Txpd2 = ps2_d_tx_2 + END + + It would result in the following device tree nodes: + + opb_ps2_dual_ref_0@a9000000 { + ranges = <0 a9000000 2000>; + // If this device had extra parameters, then they would + // go here. + ps2@0 { + compatible = "xlnx,opb-ps2-dual-ref-1.00.a"; + reg = <0 40>; + interrupt-parent = <&opb-intc>; + interrupts = <3 0>; + cell-index = <0>; + }; + ps2@1000 { + compatible = "xlnx,opb-ps2-dual-ref-1.00.a"; + reg = <1000 40>; + interrupt-parent = <&opb-intc>; + interrupts = <3 0>; + cell-index = <0>; + }; + }; + + Also, the system.mhs file defines bus attachments from the processor + to the devices. The device tree structure should reflect the bus + attachments. Again an example; this system.mhs fragment: + + BEGIN ppc405_virtex4 + PARAMETER INSTANCE = ppc405_0 + PARAMETER HW_VER = 1.01.a + BUS_INTERFACE DPLB = plb_v34_0 + BUS_INTERFACE IPLB = plb_v34_0 + END + + BEGIN opb_intc + PARAMETER INSTANCE = opb_intc_0 + PARAMETER HW_VER = 1.00.c + PARAMETER C_BASEADDR = 0xD1000FC0 + PARAMETER C_HIGHADDR = 0xD1000FDF + BUS_INTERFACE SOPB = opb_v20_0 + END + + BEGIN opb_uart16550 + PARAMETER INSTANCE = opb_uart16550_0 + PARAMETER HW_VER = 1.00.d + PARAMETER C_BASEADDR = 0xa0000000 + PARAMETER C_HIGHADDR = 0xa0001FFF + BUS_INTERFACE SOPB = opb_v20_0 + END + + BEGIN plb_v34 + PARAMETER INSTANCE = plb_v34_0 + PARAMETER HW_VER = 1.02.a + END + + BEGIN plb_bram_if_cntlr + PARAMETER INSTANCE = plb_bram_if_cntlr_0 + PARAMETER HW_VER = 1.00.b + PARAMETER C_BASEADDR = 0xFFFF0000 + PARAMETER C_HIGHADDR = 0xFFFFFFFF + BUS_INTERFACE SPLB = plb_v34_0 + END + + BEGIN plb2opb_bridge + PARAMETER INSTANCE = plb2opb_bridge_0 + PARAMETER HW_VER = 1.01.a + PARAMETER C_RNG0_BASEADDR = 0x20000000 + PARAMETER C_RNG0_HIGHADDR = 0x3FFFFFFF + PARAMETER C_RNG1_BASEADDR = 0x60000000 + PARAMETER C_RNG1_HIGHADDR = 0x7FFFFFFF + PARAMETER C_RNG2_BASEADDR = 0x80000000 + PARAMETER C_RNG2_HIGHADDR = 0xBFFFFFFF + PARAMETER C_RNG3_BASEADDR = 0xC0000000 + PARAMETER C_RNG3_HIGHADDR = 0xDFFFFFFF + BUS_INTERFACE SPLB = plb_v34_0 + BUS_INTERFACE MOPB = opb_v20_0 + END + + Gives this device tree (some properties removed for clarity): + + plb-v34-0 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "ibm,plb"; + ranges; // 1:1 translation + + plb-bram-if-cntrl-0@ffff0000 { + reg = <ffff0000 10000>; + } + + opb-v20-0 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <20000000 20000000 20000000 + 60000000 60000000 20000000 + 80000000 80000000 40000000 + c0000000 c0000000 20000000>; + + opb-uart16550-0@a0000000 { + reg = <a00000000 2000>; + }; + + opb-intc-0@d1000fc0 { + reg = <d1000fc0 20>; + }; + }; + }; + + That covers the general approach to binding xilinx IP cores into the + device tree. The following are bindings for specific devices: + + i) Xilinx ML300 Framebuffer + + Simple framebuffer device from the ML300 reference design (also on the + ML403 reference design as well as others). + + Optional properties: + - resolution = <xres yres> : pixel resolution of framebuffer. Some + implementations use a different resolution. + Default is <d#640 d#480> + - virt-resolution = <xvirt yvirt> : Size of framebuffer in memory. + Default is <d#1024 d#480>. + - rotate-display (empty) : rotate display 180 degrees. + + ii) Xilinx SystemACE + + The Xilinx SystemACE device is used to program FPGAs from an FPGA + bitstream stored on a CF card. It can also be used as a generic CF + interface device. + + Optional properties: + - 8-bit (empty) : Set this property for SystemACE in 8 bit mode + + iii) Xilinx EMAC and Xilinx TEMAC + + Xilinx Ethernet devices. In addition to general xilinx properties + listed above, nodes for these devices should include a phy-handle + property, and may include other common network device properties + like local-mac-address. + + iv) Xilinx Uartlite + + Xilinx uartlite devices are simple fixed speed serial ports. + + Requred properties: + - current-speed : Baud rate of uartlite + More devices will be defined as this spec matures. VII - Specifying interrupt information for devices ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 3/4] Device tree bindings for Xilinx devices 2007-10-23 4:27 ` [PATCH 3/4] Device tree bindings for Xilinx devices Grant Likely @ 2007-10-23 12:36 ` Josh Boyer 0 siblings, 0 replies; 7+ messages in thread From: Josh Boyer @ 2007-10-23 12:36 UTC (permalink / raw) To: Grant Likely; +Cc: linuxppc-dev, paulus, David Gibson On Mon, 22 Oct 2007 22:27:41 -0600 Grant Likely <grant.likely@secretlab•ca> wrote: > From: Grant Likely <grant.likely@secretlab•ca> > > Signed-off-by: Grant Likely <grant.likely@secretlab•ca> > Acked-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx•com> This looks pretty good to me. Acked-by: Josh Boyer <jwboyer@linux•vnet.ibm.com> josh > --- > > Documentation/powerpc/booting-without-of.txt | 261 ++++++++++++++++++++++++++ > 1 files changed, 261 insertions(+), 0 deletions(-) > > diff --git a/Documentation/powerpc/booting-without-of.txt b/Documentation/powerpc/booting-without-of.txt > index a96e853..59df69d 100644 > --- a/Documentation/powerpc/booting-without-of.txt > +++ b/Documentation/powerpc/booting-without-of.txt > @@ -52,6 +52,7 @@ Table of Contents > i) Freescale QUICC Engine module (QE) > j) CFI or JEDEC memory-mapped NOR flash > k) Global Utilities Block > + l) Xilinx IP cores > > VII - Specifying interrupt information for devices > 1) interrupts property > @@ -2242,6 +2243,266 @@ platforms are moved over to use the flattened-device-tree model. > available. > For Axon: 0x0000012a > > + l) Xilinx IP cores > + > + The Xilinx EDK toolchain ships with a set of IP cores (devices) for use > + in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range > + of standard device types (network, serial, etc.) and miscellanious > + devices (gpio, LCD, spi, etc). Also, since these devices are > + implemented within the fpga fabric every instance of the device can be > + synthesised with different options that change the behaviour. > + > + Each IP-core has a set of parameters which the FPGA designer can use to > + control how the core is synthesized. Historically, the EDK tool would > + extract the device parameters relevant to device drivers and copy them > + into an 'xparameters.h' in the form of #define symbols. This tells the > + device drivers how the IP cores are configured, but it requres the kernel > + to be recompiled every time the FPGA bitstream is resynthesized. > + > + The new approach is to export the parameters into the device tree and > + generate a new device tree each time the FPGA bitstream changes. The > + parameters which used to be exported as #defines will now become > + properties of the device node. In general, device nodes for IP-cores > + will take the following form: > + > + (name)@(base-address) { > + compatible = "xlnx,(ip-core-name)-(HW_VER)" > + [, (list of compatible devices), ...]; > + reg = <(baseaddr) (size)>; > + interrupt-parent = <&interrupt-controller-phandle>; > + interrupts = < ... >; > + xlnx,(parameter1) = "(string-value)"; > + xlnx,(parameter2) = <(int-value)>; > + }; > + > + (ip-core-name): the name of the ip block (given after the BEGIN > + directive in system.mhs). Should be in lowercase > + and all underscores '_' converted to dashes '-'. > + (name): is derived from the "PARAMETER INSTANCE" value. > + (parameter#): C_* parameters from system.mhs. The C_ prefix is > + dropped from the parameter name, the name is converted > + to lowercase and all underscore '_' characters are > + converted to dashes '-'. > + (baseaddr): the C_BASEADDR parameter. > + (HW_VER): from the HW_VER parameter. > + (size): equals C_HIGHADDR - C_BASEADDR + 1 > + > + Typically, the compatible list will include the exact IP core version > + followed by an older IP core version which implements the same > + interface or any other device with the same interface. > + > + 'reg', 'interrupt-parent' and 'interrupts' are all optional properties. > + > + For example, the following block from system.mhs: > + > + BEGIN opb_uartlite > + PARAMETER INSTANCE = opb_uartlite_0 > + PARAMETER HW_VER = 1.00.b > + PARAMETER C_BAUDRATE = 115200 > + PARAMETER C_DATA_BITS = 8 > + PARAMETER C_ODD_PARITY = 0 > + PARAMETER C_USE_PARITY = 0 > + PARAMETER C_CLK_FREQ = 50000000 > + PARAMETER C_BASEADDR = 0xEC100000 > + PARAMETER C_HIGHADDR = 0xEC10FFFF > + BUS_INTERFACE SOPB = opb_7 > + PORT OPB_Clk = CLK_50MHz > + PORT Interrupt = opb_uartlite_0_Interrupt > + PORT RX = opb_uartlite_0_RX > + PORT TX = opb_uartlite_0_TX > + PORT OPB_Rst = sys_bus_reset_0 > + END > + > + becomes the following device tree node: > + > + opb-uartlite-0@ec100000 { > + device_type = "serial"; > + compatible = "xlnx,opb-uartlite-1.00.b"; > + reg = <ec100000 10000>; > + interrupt-parent = <&opb-intc>; > + interrupts = <1 0>; // got this from the opb_intc parameters > + current-speed = <d#115200>; // standard serial device prop > + clock-frequency = <d#50000000>; // standard serial device prop > + xlnx,data-bits = <8>; > + xlnx,odd-parity = <0>; > + xlnx,use-parity = <0>; > + }; > + > + Some IP cores actually implement 2 or more logical devices. In this case, > + the device should still describe the whole IP core with a single node > + and add a child node for each logical device. The ranges property can > + be used to translate from parent IP-core to the registers of each device. > + (Note: this makes the assumption that both logical devices have the same > + bus binding. If this is not true, then separate nodes should be used for > + each logical device). The 'cell-index' property can be used to enumerate > + logical devices within an IP core. For example, the following is the > + system.mhs entry for the dual ps2 controller found on the ml403 reference > + design. > + > + BEGIN opb_ps2_dual_ref > + PARAMETER INSTANCE = opb_ps2_dual_ref_0 > + PARAMETER HW_VER = 1.00.a > + PARAMETER C_BASEADDR = 0xA9000000 > + PARAMETER C_HIGHADDR = 0xA9001FFF > + BUS_INTERFACE SOPB = opb_v20_0 > + PORT Sys_Intr1 = ps2_1_intr > + PORT Sys_Intr2 = ps2_2_intr > + PORT Clkin1 = ps2_clk_rx_1 > + PORT Clkin2 = ps2_clk_rx_2 > + PORT Clkpd1 = ps2_clk_tx_1 > + PORT Clkpd2 = ps2_clk_tx_2 > + PORT Rx1 = ps2_d_rx_1 > + PORT Rx2 = ps2_d_rx_2 > + PORT Txpd1 = ps2_d_tx_1 > + PORT Txpd2 = ps2_d_tx_2 > + END > + > + It would result in the following device tree nodes: > + > + opb_ps2_dual_ref_0@a9000000 { > + ranges = <0 a9000000 2000>; > + // If this device had extra parameters, then they would > + // go here. > + ps2@0 { > + compatible = "xlnx,opb-ps2-dual-ref-1.00.a"; > + reg = <0 40>; > + interrupt-parent = <&opb-intc>; > + interrupts = <3 0>; > + cell-index = <0>; > + }; > + ps2@1000 { > + compatible = "xlnx,opb-ps2-dual-ref-1.00.a"; > + reg = <1000 40>; > + interrupt-parent = <&opb-intc>; > + interrupts = <3 0>; > + cell-index = <0>; > + }; > + }; > + > + Also, the system.mhs file defines bus attachments from the processor > + to the devices. The device tree structure should reflect the bus > + attachments. Again an example; this system.mhs fragment: > + > + BEGIN ppc405_virtex4 > + PARAMETER INSTANCE = ppc405_0 > + PARAMETER HW_VER = 1.01.a > + BUS_INTERFACE DPLB = plb_v34_0 > + BUS_INTERFACE IPLB = plb_v34_0 > + END > + > + BEGIN opb_intc > + PARAMETER INSTANCE = opb_intc_0 > + PARAMETER HW_VER = 1.00.c > + PARAMETER C_BASEADDR = 0xD1000FC0 > + PARAMETER C_HIGHADDR = 0xD1000FDF > + BUS_INTERFACE SOPB = opb_v20_0 > + END > + > + BEGIN opb_uart16550 > + PARAMETER INSTANCE = opb_uart16550_0 > + PARAMETER HW_VER = 1.00.d > + PARAMETER C_BASEADDR = 0xa0000000 > + PARAMETER C_HIGHADDR = 0xa0001FFF > + BUS_INTERFACE SOPB = opb_v20_0 > + END > + > + BEGIN plb_v34 > + PARAMETER INSTANCE = plb_v34_0 > + PARAMETER HW_VER = 1.02.a > + END > + > + BEGIN plb_bram_if_cntlr > + PARAMETER INSTANCE = plb_bram_if_cntlr_0 > + PARAMETER HW_VER = 1.00.b > + PARAMETER C_BASEADDR = 0xFFFF0000 > + PARAMETER C_HIGHADDR = 0xFFFFFFFF > + BUS_INTERFACE SPLB = plb_v34_0 > + END > + > + BEGIN plb2opb_bridge > + PARAMETER INSTANCE = plb2opb_bridge_0 > + PARAMETER HW_VER = 1.01.a > + PARAMETER C_RNG0_BASEADDR = 0x20000000 > + PARAMETER C_RNG0_HIGHADDR = 0x3FFFFFFF > + PARAMETER C_RNG1_BASEADDR = 0x60000000 > + PARAMETER C_RNG1_HIGHADDR = 0x7FFFFFFF > + PARAMETER C_RNG2_BASEADDR = 0x80000000 > + PARAMETER C_RNG2_HIGHADDR = 0xBFFFFFFF > + PARAMETER C_RNG3_BASEADDR = 0xC0000000 > + PARAMETER C_RNG3_HIGHADDR = 0xDFFFFFFF > + BUS_INTERFACE SPLB = plb_v34_0 > + BUS_INTERFACE MOPB = opb_v20_0 > + END > + > + Gives this device tree (some properties removed for clarity): > + > + plb-v34-0 { > + #address-cells = <1>; > + #size-cells = <1>; > + device_type = "ibm,plb"; > + ranges; // 1:1 translation > + > + plb-bram-if-cntrl-0@ffff0000 { > + reg = <ffff0000 10000>; > + } > + > + opb-v20-0 { > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <20000000 20000000 20000000 > + 60000000 60000000 20000000 > + 80000000 80000000 40000000 > + c0000000 c0000000 20000000>; > + > + opb-uart16550-0@a0000000 { > + reg = <a00000000 2000>; > + }; > + > + opb-intc-0@d1000fc0 { > + reg = <d1000fc0 20>; > + }; > + }; > + }; > + > + That covers the general approach to binding xilinx IP cores into the > + device tree. The following are bindings for specific devices: > + > + i) Xilinx ML300 Framebuffer > + > + Simple framebuffer device from the ML300 reference design (also on the > + ML403 reference design as well as others). > + > + Optional properties: > + - resolution = <xres yres> : pixel resolution of framebuffer. Some > + implementations use a different resolution. > + Default is <d#640 d#480> > + - virt-resolution = <xvirt yvirt> : Size of framebuffer in memory. > + Default is <d#1024 d#480>. > + - rotate-display (empty) : rotate display 180 degrees. > + > + ii) Xilinx SystemACE > + > + The Xilinx SystemACE device is used to program FPGAs from an FPGA > + bitstream stored on a CF card. It can also be used as a generic CF > + interface device. > + > + Optional properties: > + - 8-bit (empty) : Set this property for SystemACE in 8 bit mode > + > + iii) Xilinx EMAC and Xilinx TEMAC > + > + Xilinx Ethernet devices. In addition to general xilinx properties > + listed above, nodes for these devices should include a phy-handle > + property, and may include other common network device properties > + like local-mac-address. > + > + iv) Xilinx Uartlite > + > + Xilinx uartlite devices are simple fixed speed serial ports. > + > + Requred properties: > + - current-speed : Baud rate of uartlite > + > More devices will be defined as this spec matures. > > VII - Specifying interrupt information for devices > ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 4/4] Uartlite: speed up console output 2007-10-23 4:27 [PATCH 0/4] Misc patches for the 2.6.24 merge window Grant Likely ` (2 preceding siblings ...) 2007-10-23 4:27 ` [PATCH 3/4] Device tree bindings for Xilinx devices Grant Likely @ 2007-10-23 4:27 ` Grant Likely 2007-10-31 14:45 ` Peter Korsgaard 3 siblings, 1 reply; 7+ messages in thread From: Grant Likely @ 2007-10-23 4:27 UTC (permalink / raw) To: paulus, linuxppc-dev; +Cc: David Gibson From: Grant Likely <grant.likely@secretlab•ca> Change the wait_tx routine to call cpu_relax() instead of udelay() to reduce console output latency and test for the TXFULL bit instead of TXEMPTY. That way the FIFO doesn't need to by 100% flushed before writing the next character. Signed-off-by: Grant Likely <grant.likely@secretlab•ca> --- drivers/serial/uartlite.c | 10 ++++++---- 1 files changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/serial/uartlite.c b/drivers/serial/uartlite.c index dfef83f..a85f2d3 100644 --- a/drivers/serial/uartlite.c +++ b/drivers/serial/uartlite.c @@ -329,12 +329,14 @@ static struct uart_ops ulite_ops = { static void ulite_console_wait_tx(struct uart_port *port) { int i; + u8 val; - /* wait up to 10ms for the character(s) to be sent */ - for (i = 0; i < 10000; i++) { - if (readb(port->membase + ULITE_STATUS) & ULITE_STATUS_TXEMPTY) + /* Spin waiting for TX fifo to have space available */ + for (i = 0; i < 100000; i++) { + val = readb(port->membase + ULITE_STATUS); + if ((val & ULITE_STATUS_TXFULL) == 0) break; - udelay(1); + cpu_relax(); } } ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 4/4] Uartlite: speed up console output 2007-10-23 4:27 ` [PATCH 4/4] Uartlite: speed up console output Grant Likely @ 2007-10-31 14:45 ` Peter Korsgaard 0 siblings, 0 replies; 7+ messages in thread From: Peter Korsgaard @ 2007-10-31 14:45 UTC (permalink / raw) To: Grant Likely; +Cc: linuxppc-dev, paulus, David Gibson >>>>> "Grant" == Grant Likely <grant.likely@secretlab•ca> writes: Hi, Grant> From: Grant Likely <grant.likely@secretlab•ca> Grant> Change the wait_tx routine to call cpu_relax() instead of udelay() to Grant> reduce console output latency and test for the TXFULL bit instead of Grant> TXEMPTY. That way the FIFO doesn't need to by 100% flushed before Grant> writing the next character. Sorry for the slow response - I had a misunderstanding with the phone company, and I'm now without inet :/ Looks good to me. I gave it a quick spin to check the speed difference: Old: [ 0.453101] Freeing unused kernel memory: 52k init New: [ 0.433686] Freeing unused kernel memory: 52k init So it shaves off ~20ms (~4%) of bootup. It ofcause means that the console routines return before the data is actually transmitted on the wire, but I guess you have to screw seriously up for the UART to die before emptying it's FIFO. Grant> Signed-off-by: Grant Likely <grant.likely@secretlab•ca> Acked-by: Peter Korsgaard <jacmet@sunsite•dk> -- Bye, Peter Korsgaard ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2007-10-31 14:45 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2007-10-23 4:27 [PATCH 0/4] Misc patches for the 2.6.24 merge window Grant Likely 2007-10-23 4:27 ` [PATCH 1/4] bootwrapper: Allow wrapper script to execute verbosely Grant Likely 2007-10-23 4:27 ` [PATCH 2/4] bootwrapper: Bail from script if any command fails Grant Likely 2007-10-23 4:27 ` [PATCH 3/4] Device tree bindings for Xilinx devices Grant Likely 2007-10-23 12:36 ` Josh Boyer 2007-10-23 4:27 ` [PATCH 4/4] Uartlite: speed up console output Grant Likely 2007-10-31 14:45 ` Peter Korsgaard
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