From: Michael Ellerman <mpe@ellerman•id.au>
To: Athira Rajeev <atrajeev@linux•vnet.ibm.com>,
acme@kernel•org, jolsa@kernel•org
Cc: kjain@linux•ibm.com, maddy@linux•ibm.com,
linuxppc-dev@lists•ozlabs.org, rnsastry@linux•ibm.com
Subject: Re: [PATCH 1/2] powerpc/perf: Expose instruction and data address registers as part of extended regs
Date: Wed, 08 Sep 2021 15:17:15 +1000 [thread overview]
Message-ID: <87pmtjmysk.fsf@mpe.ellerman.id.au> (raw)
In-Reply-To: <1624200360-1429-2-git-send-email-atrajeev@linux.vnet.ibm.com>
Athira Rajeev <atrajeev@linux•vnet.ibm.com> writes:
> Patch adds support to include Sampled Instruction Address Register
> (SIAR) and Sampled Data Address Register (SDAR) SPRs as part of extended
> registers. Update the definition of PERF_REG_PMU_MASK_300/31 and
> PERF_REG_EXTENDED_MAX to include these SPR's.
>
> Signed-off-by: Athira Rajeev <atrajeev@linux•vnet.ibm.com>
> ---
> arch/powerpc/include/uapi/asm/perf_regs.h | 12 +++++++-----
> arch/powerpc/perf/perf_regs.c | 4 ++++
> 2 files changed, 11 insertions(+), 5 deletions(-)
>
...
> diff --git a/arch/powerpc/perf/perf_regs.c b/arch/powerpc/perf/perf_regs.c
> index b931eed..51d31b6 100644
> --- a/arch/powerpc/perf/perf_regs.c
> +++ b/arch/powerpc/perf/perf_regs.c
> @@ -90,7 +90,11 @@ static u64 get_ext_regs_value(int idx)
> return mfspr(SPRN_SIER2);
> case PERF_REG_POWERPC_SIER3:
> return mfspr(SPRN_SIER3);
> + case PERF_REG_POWERPC_SDAR:
> + return mfspr(SPRN_SDAR);
> #endif
> + case PERF_REG_POWERPC_SIAR:
> + return mfspr(SPRN_SIAR);
> default: return 0;
> }
This file is built for all powerpc configs that have PERF_EVENTS. Which
includes CPUs that don't have SDAR or SIAR.
Don't we need checks in perf_reg_value() like we do for SIER?
I guess we already got this wrong when we added the Power10 registers,
SIER2/3 etc.
cheers
next prev parent reply other threads:[~2021-09-08 5:18 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-20 14:45 [PATCH 0/2] powerpc/perf: Add instruction and data address registers to extended regs Athira Rajeev
2021-06-20 14:45 ` [PATCH 1/2] powerpc/perf: Expose instruction and data address registers as part of " Athira Rajeev
2021-09-08 5:17 ` Michael Ellerman [this message]
2021-09-09 2:48 ` Athira Rajeev
2021-09-20 7:13 ` Michael Ellerman
2021-09-21 3:01 ` Athira Rajeev
2021-06-20 14:46 ` [PATCH 2/2] tools/perf: Add perf tools support to expose " Athira Rajeev
2021-06-21 4:09 ` [PATCH 0/2] powerpc/perf: Add instruction and data address registers to " Nageswara Sastry
2021-09-02 7:34 ` kajoljain
2021-09-06 2:43 ` Athira Rajeev
2021-09-11 19:09 ` Arnaldo Carvalho de Melo
2021-09-20 6:54 ` Michael Ellerman
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=87pmtjmysk.fsf@mpe.ellerman.id.au \
--to=mpe@ellerman$(echo .)id.au \
--cc=acme@kernel$(echo .)org \
--cc=atrajeev@linux$(echo .)vnet.ibm.com \
--cc=jolsa@kernel$(echo .)org \
--cc=kjain@linux$(echo .)ibm.com \
--cc=linuxppc-dev@lists$(echo .)ozlabs.org \
--cc=maddy@linux$(echo .)ibm.com \
--cc=rnsastry@linux$(echo .)ibm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox