From: Michael Ellerman <mpe@ellerman•id.au>
To: Michael Neuling <mikey@neuling•org>, linuxppc-dev@lists•ozlabs.org
Cc: benh@kernel•crashing.org, paulus@samba•org, sam.bobroff@au1•ibm.com
Subject: Re: [PATCH] powernv: Properly mask POWER9 DD1 PVR for different chip types
Date: Thu, 08 Jun 2017 13:44:59 +1000 [thread overview]
Message-ID: <87poefdtxg.fsf@concordia.ellerman.id.au> (raw)
In-Reply-To: <1496882650.31524.14.camel@neuling.org>
Michael Neuling <mikey@neuling•org> writes:
> On Wed, 2017-06-07 at 17:24 +1000, Michael Ellerman wrote:
>> Michael Neuling <mikey@neuling•org> writes:
>>=20
>> > Bits 48:51 in the PVR for POWER9 represent different chip types (scale
>> > up vs out and 12 vs 24 core). Current chips have 0 here, but could be
>> > non-zero in the future.
>> >=20
>> > This changes the POWER9 DD1 mask to correctly ignore these bits 48:51.
>> >=20
>> > Signed-off-by: Michael Neuling <mikey@neuling•org>
>> > ---
>> > =C2=A0arch/powerpc/kernel/cputable.c | 4 ++--
>> > =C2=A01 file changed, 2 insertions(+), 2 deletions(-)
>>=20
>> Presumably we should backport this?
>
> Actually, we need to scrap this patch.
>
> Looks like the scale up version will be marked as DD1, but it won't need =
these
> workarounds. So we need it to match on the other POWER9 entry.
OK.
/giphy "dumpster fire"
cheers
prev parent reply other threads:[~2017-06-08 3:45 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-07 4:11 [PATCH] powernv: Properly mask POWER9 DD1 PVR for different chip types Michael Neuling
2017-06-07 7:24 ` Michael Ellerman
2017-06-08 0:44 ` Michael Neuling
2017-06-08 3:44 ` Michael Ellerman [this message]
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