Subject: Re: [RFC] powerpc/mm: Enable TLB flush during native_register_proc_table()

From: "Aneesh Kumar K.V" <[email-masked]>
Date: Mon, 15 Jan 2018 11:43:49 +0530

Anshuman Khandual <[email-masked]> writes:

> From: Anshuman Khandual <[email-masked]>
>
> Any changes to the partition table must be followed by appropriate TLB
> flush which is not happening at present in native_register_proc_table()
> path. Fix this by calling mmu_partition_table_set_entry() which does
> take care of TLB flushing after the partition table update.
>
> Signed-off-by: Anshuman Khandual <[email-masked]>
> ---
> - From code inspection
> - Compile, boot tested without CONFIG_PPC_RADIX_MMU
> - Though it seems to be not getting called from any where

For hash the patb1 is zero and hence it is not called. This is left over
from the segment table implementation. I guess we can remove
native_register_proc_table.

>
>  arch/powerpc/mm/hash_native_64.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
> index 640cf56..89be5a6 100644
> --- a/arch/powerpc/mm/hash_native_64.c
> +++ b/arch/powerpc/mm/hash_native_64.c
> @@ -758,12 +758,14 @@ static void native_flush_hash_range(unsigned long number, int local)
>  static int native_register_proc_table(unsigned long base, unsigned long page_size,
>  				      unsigned long table_size)
>  {
> -	unsigned long patb1 = base << 25; /* VSID */
> +	unsigned long patb0, patb1;
>  
> +	patb1 = base << 25;	    /* VSID */
>  	patb1 |= (page_size << 5);  /* sllp */
>  	patb1 |= table_size;
>  
> -	partition_tb->patb1 = cpu_to_be64(patb1);
> +	patb0 = be64_to_cpu(partition_tb[0].patb0);
> +	mmu_partition_table_set_entry(0, patb0, patb1);
>  	return 0;
>  }
>  
> -- 
> 1.8.3.1