Subject: Re: [PATCH 4/4] powerpc/64s: Use POWER10 stsync barrier for wmb()

From: Michael Ellerman <[email-masked]>
Date: Wed, 14 Jun 2023 15:56:57 +1000

Michael Ellerman <[email-masked]> writes:
> Nicholas Piggin <[email-masked]> writes:
>> The most expensive ordering for hwsync to provide is the store-load
>> barrier, because all prior stores have to be drained to the caches
>> before subsequent instructions can complete.
>>
>> stsync just orders stores which means it can just be a barrer that
>> goes down the store queue and orders draining, and does not prevent
>> completion of subsequent instructions. So it should be faster than
>> hwsync.
>>
>> Use stsync for wmb(). Older processors that don't recognise the SC
>> field should treat this as hwsync.
>
> qemu (7.1) emulating ppc64e does not :/
>
>   mpic: Setting up MPIC " OpenPIC  " version 1.2 at fe0040000, max 1 CPUs
>   mpic: ISU size: 256, shift: 8, mask: ff
>   mpic: Initializing for 256 sources
>   Oops: Exception in kernel mode, sig: 4 [#1]
..
>
> I guess just put it behind an #ifdef 64S.

That doesn't work because qemu emulating a G5 also doesn't accept it.

So either we need to get qemu updated and wait a while for that to
percolate, or do some runtime patching of wmbs in the kernel >_<

cheers