Subject: Re: [RFC] uartlite driver MicroBlaze compatability

From: Peter Korsgaard <[email-masked]>
Date: Wed, 02 May 2007 16:09:07 +0200

>>>>> "GL" == Grant Likely <[email-masked]> writes:

Hi,

GL> Hmm, I think I was smoking something last night.

;)

GL>  Address used for 8 bit access should not be affected by CPU
GL> endianess.  After David's comments, I reread the uartlite
GL> documentation.  The current design is definately for 32bit OPB bus
GL> connections, but it looks like there is a posibility for xilinx to
GL> add a 16 or 8 bit attachment.  Since the uartlite design
GL> explicitly supports 8, 16 and 32 bit access, sticking with 8 bit
GL> io may be the safest.  However, I still think the application of
GL> the 3 byte offset should be done in the driver, and not in the
GL> platform bus registration.

That would effectively make the driver big endian only. What if Xilinx
would come out with a FPGA with a ARM core in it?

GL> I've reworked the patch with the following changes - remove 3 byte
GL> offset from platform bus registration.  - added ulite_in/ulite_out
GL> macros to make changing bus attachment details simpler if xilinx
GL> changes the uartlite design.  - stick with 8 bit IO.

Russell didn't like those accessor macros back when it was submitted
last year:

http://thread.gmane.org/gmane.linux.serial/1237/focus=1251

-- 
Bye, Peter Korsgaard