From: Michael Ellerman <mpe@ellerman•id.au>
To: Athira Rajeev <atrajeev@linux•vnet.ibm.com>,
Paul Mackerras <paulus@ozlabs•org>
Cc: ego@linux•vnet.ibm.com, Michael Neuling <mikey@neuling•org>,
maddy@linux•vnet.ibm.com, kvm@vger•kernel.org,
kvm-ppc@vger•kernel.org, svaidyan@in•ibm.com, acme@kernel•org,
jolsa@kernel•org, linuxppc-dev@lists•ozlabs.org
Subject: Re: [v3 02/15] KVM: PPC: Book3S HV: Cleanup updates for kvm vcpu MMCR
Date: Wed, 22 Jul 2020 14:37:35 +1000 [thread overview]
Message-ID: <87y2ncqi5s.fsf@mpe.ellerman.id.au> (raw)
In-Reply-To: <B83C440A-1AC4-4737-8AB1-EB9A6B8A474B@linux.vnet.ibm.com>
Athira Rajeev <atrajeev@linux•vnet.ibm.com> writes:
>> On 21-Jul-2020, at 9:24 AM, Paul Mackerras <paulus@ozlabs•org> wrote:
>> On Fri, Jul 17, 2020 at 10:38:14AM -0400, Athira Rajeev wrote:
>>> Currently `kvm_vcpu_arch` stores all Monitor Mode Control registers
>>> in a flat array in order: mmcr0, mmcr1, mmcra, mmcr2, mmcrs
>>> Split this to give mmcra and mmcrs its own entries in vcpu and
>>> use a flat array for mmcr0 to mmcr2. This patch implements this
>>> cleanup to make code easier to read.
>>
>> Changing the way KVM stores these values internally is fine, but
>> changing the user ABI is not. This part:
>>
>>> diff --git a/arch/powerpc/include/uapi/asm/kvm.h b/arch/powerpc/include/uapi/asm/kvm.h
>>> index 264e266..e55d847 100644
>>> --- a/arch/powerpc/include/uapi/asm/kvm.h
>>> +++ b/arch/powerpc/include/uapi/asm/kvm.h
>>> @@ -510,8 +510,8 @@ struct kvm_ppc_cpu_char {
>>>
>>> #define KVM_REG_PPC_MMCR0 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x10)
>>> #define KVM_REG_PPC_MMCR1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x11)
>>> -#define KVM_REG_PPC_MMCRA (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x12)
>>> -#define KVM_REG_PPC_MMCR2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x13)
>>> +#define KVM_REG_PPC_MMCR2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x12)
>>> +#define KVM_REG_PPC_MMCRA (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x13)
>>
>> means that existing userspace programs that used to work would now be
>> broken. That is not acceptable (breaking the user ABI is only ever
>> acceptable with a very compelling reason). So NAK to this part of the
>> patch.
>
> Hi Paul
>
> Thanks for checking the patch. I understood your point on user ABI breakage that this particular change can cause.
> I will retain original KVM_REG_PPC_MMCRA and KVM_REG_PPC_MMCR2 order in `kvm.h`
> And with that, additionally I will need below change ( on top of current patch ) for my clean up updates for kvm cpu MMCR to work,
> Because now mmcra and mmcrs will have its own entries in vcpu and is not part of the mmcr[] array
> Please suggest if this looks good
I did the same patch I think in my testing branch, it's here:
https://github.com/linuxppc/linux/commit/daea78154eff1b7e2f36be05a8f95feb5a588912
Can you please check that matches what you sent.
cheers
> diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
> index 3f90eee261fc..b10bb404f0d5 100644
> --- a/arch/powerpc/kvm/book3s_hv.c
> +++ b/arch/powerpc/kvm/book3s_hv.c
> @@ -1679,10 +1679,13 @@ static int kvmppc_get_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
> case KVM_REG_PPC_UAMOR:
> *val = get_reg_val(id, vcpu->arch.uamor);
> break;
> - case KVM_REG_PPC_MMCR0 ... KVM_REG_PPC_MMCR2:
> + case KVM_REG_PPC_MMCR0 ... KVM_REG_PPC_MMCR1:
> i = id - KVM_REG_PPC_MMCR0;
> *val = get_reg_val(id, vcpu->arch.mmcr[i]);
> break;
> + case KVM_REG_PPC_MMCR2:
> + *val = get_reg_val(id, vcpu->arch.mmcr[2]);
> + break;
> case KVM_REG_PPC_MMCRA:
> *val = get_reg_val(id, vcpu->arch.mmcra);
> break;
> @@ -1906,10 +1909,13 @@ static int kvmppc_set_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
> case KVM_REG_PPC_UAMOR:
> vcpu->arch.uamor = set_reg_val(id, *val);
> break;
> - case KVM_REG_PPC_MMCR0 ... KVM_REG_PPC_MMCR2:
> + case KVM_REG_PPC_MMCR0 ... KVM_REG_PPC_MMCR1:
> i = id - KVM_REG_PPC_MMCR0;
> vcpu->arch.mmcr[i] = set_reg_val(id, *val);
> break;
> + case KVM_REG_PPC_MMCR2:
> + vcpu->arch.mmcr[2] = set_reg_val(id, *val);
> + break;
> case KVM_REG_PPC_MMCRA:
> vcpu->arch.mmcra = set_reg_val(id, *val);
> break;
> —
>
>
>>
>> Regards,
>> Paul.
next prev parent reply other threads:[~2020-07-22 4:57 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-17 14:38 [v3 00/15] powerpc/perf: Add support for power10 PMU Hardware Athira Rajeev
2020-07-17 14:38 ` [v3 01/15] powerpc/perf: Update cpu_hw_event to use `struct` for storing MMCR registers Athira Rajeev
2020-07-21 3:42 ` Jordan Niethe
2020-07-22 2:15 ` Athira Rajeev
2020-07-17 14:38 ` [v3 02/15] KVM: PPC: Book3S HV: Cleanup updates for kvm vcpu MMCR Athira Rajeev
2020-07-21 3:54 ` Paul Mackerras
2020-07-22 2:09 ` Athira Rajeev
2020-07-22 4:37 ` Michael Ellerman [this message]
2020-07-22 5:49 ` Athira Rajeev
2020-07-22 4:54 ` Paul Mackerras
2020-07-22 6:03 ` Madhavan Srinivasan
2020-07-22 4:38 ` Michael Ellerman
2020-07-17 14:38 ` [v3 03/15] powerpc/perf: Update Power PMU cache_events to u64 type Athira Rajeev
2020-07-17 14:38 ` [v3 04/15] powerpc/perf: Add support for ISA3.1 PMU SPRs Athira Rajeev
2020-07-22 4:18 ` Jordan Niethe
2020-07-22 8:07 ` Athira Rajeev
2020-07-22 10:52 ` Jordan Niethe
2020-07-22 12:03 ` Michael Ellerman
2020-07-17 14:38 ` [v3 05/15] KVM: PPC: Book3S HV: Save/restore new PMU registers Athira Rajeev
2020-07-17 14:38 ` [v3 06/15] powerpc/xmon: Add PowerISA v3.1 PMU SPRs Athira Rajeev
2020-07-17 14:38 ` [v3 07/15] powerpc/perf: Add power10_feat to dt_cpu_ftrs Athira Rajeev
2020-07-22 4:41 ` Jordan Niethe
2020-07-22 7:55 ` Athira Rajeev
2020-07-22 10:39 ` Michael Ellerman
2020-07-22 10:49 ` Jordan Niethe
2020-07-22 12:28 ` Athira Rajeev
2020-07-17 14:38 ` [v3 08/15] powerpc/perf: power10 Performance Monitoring support Athira Rajeev
2020-07-17 14:38 ` [v3 09/15] powerpc/perf: Ignore the BHRB kernel address filtering for P10 Athira Rajeev
2020-07-17 14:38 ` [v3 10/15] powerpc/perf: Add Power10 BHRB filter support for PERF_SAMPLE_BRANCH_IND_CALL/COND Athira Rajeev
2020-07-17 14:38 ` [v3 11/15] powerpc/perf: BHRB control to disable BHRB logic when not used Athira Rajeev
2020-07-20 10:05 ` Gautham R Shenoy
2020-07-23 1:26 ` Jordan Niethe
2020-07-23 1:28 ` Jordan Niethe
2020-07-17 14:38 ` [v3 12/15] powerpc/perf: Add support for outputting extended regs in perf intr_regs Athira Rajeev
2020-07-19 11:17 ` kernel test robot
2020-07-20 8:09 ` Athira Rajeev
2020-07-21 6:02 ` kajoljain
2020-07-23 5:44 ` kajoljain
2020-07-23 14:56 ` Arnaldo Carvalho de Melo
2020-07-24 8:25 ` Athira Rajeev
2020-07-24 12:26 ` Ravi Bangoria
2020-07-24 18:13 ` Athira Rajeev
2020-07-17 14:38 ` [v3 13/15] tools/perf: Add perf tools support for extended register capability in powerpc Athira Rajeev
2020-07-21 6:03 ` kajoljain
2020-07-24 11:02 ` Ravi Bangoria
2020-07-24 18:02 ` Athira Rajeev
2020-07-17 14:38 ` [v3 14/15] powerpc/perf: Add extended regs support for power10 platform Athira Rajeev
2020-07-21 6:03 ` kajoljain
2020-07-17 14:38 ` [v3 15/15] tools/perf: Add perf tools support for extended regs in power10 Athira Rajeev
2020-07-21 6:04 ` kajoljain
2020-07-24 13:24 ` [v3 00/15] powerpc/perf: Add support for power10 PMU Hardware Michael Ellerman
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=87y2ncqi5s.fsf@mpe.ellerman.id.au \
--to=mpe@ellerman$(echo .)id.au \
--cc=acme@kernel$(echo .)org \
--cc=atrajeev@linux$(echo .)vnet.ibm.com \
--cc=ego@linux$(echo .)vnet.ibm.com \
--cc=jolsa@kernel$(echo .)org \
--cc=kvm-ppc@vger$(echo .)kernel.org \
--cc=kvm@vger$(echo .)kernel.org \
--cc=linuxppc-dev@lists$(echo .)ozlabs.org \
--cc=maddy@linux$(echo .)vnet.ibm.com \
--cc=mikey@neuling$(echo .)org \
--cc=paulus@ozlabs$(echo .)org \
--cc=svaidyan@in$(echo .)ibm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox