Subject: Re[2]: [PATCH] powerpc: add support for PAGE_SIZEs greater than 4KB for

From: Yuri Tikhonov <[email-masked]>
Date: Fri, 12 Sep 2008 03:20:15 +0400

Hello Prodyut,

Thanks for your comments. Some answers below.

On Friday, September 12, 2008 you wrote:

>>        /*
>>         * Create WS1. This is the faulting address (EPN),
>>         * page size, and valid flag.
>>         */
>> -       li      r11,PPC44x_TLB_VALID | PPC44x_TLB_4K
>> +       li      r11,PPC44x_TLB_VALID | PPC44x_TLBE_SIZE
>>        rlwimi  r10,r11,0,20,31                 /* Insert valid and page size*/
>>        tlbwe   r10,r13,PPC44x_TLB_PAGEID       /* Write PAGEID */
>>

> Change
>>        rlwimi  r10,r11,0,20,31                 /* Insert valid and page size*/
> to
>>        rlwimi  r10,r11,0,PPC44x_PTE_ADD_M1,31                 /* Insert valid and page size*/

 Agree. We'll fix this.

 I guess this works for us, because we used the large EPN mask here
which covered more bits in EPN field of TLB entries, than it was
required for 16/64/256K PAGE_SIZE cases:

TLB Word 0 / bits 0..21:   EPN (Effective Page Number) [from 4 to 22 bits]
TLB Word 0 / bit 22 :      V (Valid bit) [1 bit]
TLB Word 0 / bits 24..27 : SIZE (Page Size) [4 bits]

 Thus, doing 'rlwimi' we masked our V/SIZE bits and cleared EPN for
all 4/16/64/256K PAGE_SIZE cases.

 Regards, Yuri

 --
 Yuri Tikhonov, Senior Software Engineer
 Emcraft Systems, www.emcraft.com