From: Peter Zijlstra <peterz@infradead•org>
To: Michael Ellerman <mpe@ellerman•id.au>
Cc: mark.rutland@arm•com, atrajeev@linux•vnet.ibm.com,
ak@linux•intel.com, daniel@iogearbox•net, rnsastry@linux•ibm.com,
alexander.shishkin@linux•intel.com,
Kajol Jain <kjain@linux•ibm.com>,
linux-kernel@vger•kernel.org, acme@kernel•org, ast@kernel•org,
linux-perf-users@vger•kernel.org, yao.jin@linux•intel.com,
mingo@redhat•com, paulus@samba•org, maddy@linux•ibm.com,
jolsa@kernel•org, namhyung@kernel•org, songliubraving@fb•com,
linuxppc-dev@lists•ozlabs.org, kan.liang@linux•intel.com
Subject: Re: [PATCH 1/3] perf: Add macros to specify onchip L2/L3 accesses
Date: Tue, 14 Sep 2021 13:49:37 +0200 [thread overview]
Message-ID: <YUCMUZbchMjD54eY@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <87k0jjl9sp.fsf@mpe.ellerman.id.au>
On Tue, Sep 14, 2021 at 08:40:38PM +1000, Michael Ellerman wrote:
> Peter Zijlstra <peterz@infradead•org> writes:
> > I'm thinking we ought to keep hops as steps along the NUMA fabric, with
> > 0 hops being the local node. That only gets us:
> >
> > L2, remote=0, hops=HOPS_0 -- our L2
> > L2, remote=1, hops=HOPS_0 -- L2 on the local node but not ours
> > L2, remote=1, hops!=HOPS_0 -- L2 on a remote node
>
> Hmm. I'm not sure about tying it directly to NUMA hops. I worry we're
> going to see more and more systems where there's a hierarchy within the
> chip/package, in addition to the traditional NUMA hierarchy.
>
> Although then I guess it becomes a question of what exactly is a NUMA
> hop, maybe the answer is that on those future systems those
> intra-chip/package hops should be represented as NUMA hops.
>
> It's not like we have a hard definition of what a NUMA hop is?
Not really, typically whatever the BIOS/DT/whatever tables tell us. I
think in case of Power you're mostly making things up in software :-)
But yeah, I think we have plenty wriggle room there.
next prev parent reply other threads:[~2021-09-14 11:50 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-04 6:49 [PATCH 1/3] perf: Add macros to specify onchip L2/L3 accesses Kajol Jain
2021-09-04 6:49 ` [PATCH 2/3] " Kajol Jain
2021-09-04 6:49 ` [PATCH 3/3] powerpc/perf: Fix data source encodings for power10 Kajol Jain
2021-09-08 7:17 ` [PATCH 1/3] perf: Add macros to specify onchip L2/L3 accesses Michael Ellerman
2021-09-08 9:26 ` Peter Zijlstra
2021-09-09 12:45 ` Michael Ellerman
2021-09-09 14:36 ` Peter Zijlstra
2021-09-14 10:40 ` Michael Ellerman
2021-09-14 11:49 ` Peter Zijlstra [this message]
2021-09-16 10:57 ` Michael Ellerman
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