Subject: Re: [PATCH v14 06/15] clk: Add Lynx 10G SerDes PLL driver

From: Vinod Koul <[email-masked]>
Date: Tue, 9 May 2023 18:30:16 +0530

On 08-05-23, 11:31, Sean Anderson wrote:
> On 5/8/23 05:15, Vinod Koul wrote:

> >> +int lynx_clks_init(struct device *dev, struct regmap *regmap,
> >> +		   struct clk *plls[2], struct clk *ex_dlys[2], bool compat);
> > 
> > so you have an exported symbol for clk driver init in phy driver header?
> > can you please explain why..?
> 
> So that it can be called at the appropriate time during the phy's probe function.
> 
> This is really an integral part of the phy driver, but I was directed to split it
> off and put it in another subsystem's directory.

That is right clock should be belong to clk driver. IIUC the hardware is
phy along with clocks and you are doing the clk init. I think that may
not be correct model, you should really have a device tree node to
represent the clock and the phy node

What stops this from being modelled as it is in the hardware?

-- 
~Vinod