From: Johan Hovold <johan@kernel•org>
To: Bjorn Helgaas <helgaas@kernel•org>
Cc: linux-pci@vger•kernel.org,
Manivannan Sadhasivam <manivannan.sadhasivam@oss•qualcomm.com>,
Christian Zigotzky <chzigotzky@xenosoft•de>,
FUKAUMI Naoki <naoki@radxa•com>,
Herve Codina <herve.codina@bootlin•com>,
Diederik de Haas <diederik@cknow-tech•com>,
Dragan Simic <dsimic@manjaro•org>,
linuxppc-dev@lists•ozlabs.org,
linux-rockchip@lists•infradead.org, linux-kernel@vger•kernel.org,
Bjorn Helgaas <bhelgaas@google•com>,
Shawn Lin <shawn.lin@rock-chips•com>, Frank Li <Frank.li@nxp•com>
Subject: Re: [PATCH] PCI/ASPM: Enable only L0s and L1 for devicetree platforms
Date: Mon, 27 Oct 2025 11:00:48 +0100 [thread overview]
Message-ID: <aP9C0H_2XVk6MiLV@hovoldconsulting.com> (raw)
In-Reply-To: <20251024203924.GA1361677@bhelgaas>
On Fri, Oct 24, 2025 at 03:39:24PM -0500, Bjorn Helgaas wrote:
> On Fri, Oct 24, 2025 at 05:20:33PM +0200, Johan Hovold wrote:
> > On Fri, Oct 24, 2025 at 05:12:38PM +0200, Johan Hovold wrote:
> > > Note that this will regress ASPM on Qualcomm platforms further by
> > > disabling L1SS for devices that do not use pwrctrl (e.g. NVMe). ASPM
> > > with pwrctrl is already broken since 6.15. [1]
> >
> > Actually, the 6.15 regression was fixed in 6.18-rc1 by the offending
> > commit, but pwrctrl devices will now also regress again.
> >
> > > Reverting also a729c1664619 ("PCI: qcom: Remove custom ASPM enablement
> > > code") should avoid the new regression until a proper fix for the 6.15
> > > regression is in place.
>
> Help me think through this. I just sent a pull request [2] that
> includes df5192d9bb0e ("PCI/ASPM: Enable only L0s and L1 for
> devicetree platforms"). If all goes well, v6.18-rc3 will enable L0s
> and L1 (but not L1SS) on Qualcomm platforms.
>
> IIUC, if we then revert a729c1664619 ("PCI: qcom: Remove custom ASPM
> enablement code"), it will enable L1SS again, but since this is done
> in a dw_pcie_host_ops .post_init() hook, L1SS will only be enabled for
> devices powered on at qcom-pcie probe time. It will *not* be enabled
> for pwrctrl devices because .post_init() was run when those devices
> were powered off.
Correct.
> I think this is the same as in v6.17. v6.18-rc1 enabled L1SS for
> everything, including pwrctrl devices, because it was done in the PCI
> enumeration path, not the host controller probe path. I think that
> enumeration is the right place to do this, but we need to figure out
> how to do it in a generic way. At a minimum, we need to know that
> CLKREQ# is supported, and some platforms like dw-rockchip also need
> device-specific configuration [3].
>
> Bottom line, I think we need to revert a729c1664619 for v6.18 to get
> all ASPM states including L1SS enabled on Qualcomm platforms for
> non-pwrctrl devices. I'll post a patch for this.
Right, that would at least restore the 6.17 state of things with respect
to Qualcomm machines.
> Then try to figure out how to make this work for pwrctrl devices for
> v6.19. Does this sound right?
Yes, unless you can come up with a simple way to enable L1SS during
enumeration on Qualcomm platforms, for example, using a driver callback
that returns true for platforms using the 1.9.0 ops to indicate that
L1SS is supported. That should address also the 6.15 pwrctrl regression.
Johan
next prev parent reply other threads:[~2025-10-27 10:01 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-23 18:06 [PATCH] PCI/ASPM: Enable only L0s and L1 for devicetree platforms Bjorn Helgaas
2025-10-23 18:25 ` Bjorn Helgaas
2025-10-23 19:59 ` Diederik de Haas
2025-10-23 20:39 ` Bjorn Helgaas
2025-10-24 4:28 ` Christian Zigotzky
2025-10-23 18:27 ` Dragan Simic
2025-10-23 20:37 ` Bjorn Helgaas
2025-10-24 15:12 ` Johan Hovold
2025-10-24 15:20 ` Johan Hovold
2025-10-24 20:39 ` Bjorn Helgaas
2025-10-27 10:00 ` Johan Hovold [this message]
2025-10-27 17:12 ` Christian Zigotzky
2025-10-28 23:33 ` Bjorn Helgaas
2025-10-29 5:47 ` Christian Zigotzky
2025-10-29 15:59 ` Bjorn Helgaas
2025-10-29 17:25 ` Bjorn Helgaas
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