Subject: Allowing i-side updates of TLB on 4xx/book-e

From: Kumar Gala <[email-masked]>
Date: Thu, 3 Mar 2005 19:03:51 -0600

Paul,

I know its been forever since you looked at ppc32 and even longer for 
4xx/booke :)  I did have a question regarding some code on the i-side 
TLB faults in do_page_fault:

                 /* Since 4xx/Book-E supports per-page execute 
permission,
                  * we lazily flush dcache to icache. */
                 ptep = NULL;
                 if (get_pteptr(mm, address, &ptep) && 
pte_present(*ptep)) {
                         struct page *page = pte_page(*ptep);

                         if (! test_bit(PG_arch_1, &page->flags)) {
                                 flush_dcache_icache_page(page);
                                 set_bit(PG_arch_1, &page->flags);
                         }
                         pte_update(ptep, 0, _PAGE_HWEXEC);
                         _tlbie(address);
                         pte_unmap(ptep);
                         up_read(&mm->mmap_sem);
                         return 0;
                 }

Is there a reason we don't allow preloading of the I-side TLB entry 
that we just updated, rather than doing the _tlbie?  We have to figure 
that we are about to take another I-TLB miss to reload the entry we 
just got this InstructionStorage fault for.  Is there something I'm 
missing?

thanks

- kumar