From: Stewart Smith <stewart@linux•vnet.ibm.com>
To: Samuel Mendoza-Jonas <sam.mj@au1•ibm.com>, linuxppc-dev@ozlabs•org
Cc: Samuel Mendoza-Jonas <sam.mj@au1•ibm.com>
Subject: Re: [PATCH 2/2] powerpc/kexec: Reset HILE before kexec_sequence
Date: Wed, 08 Jul 2015 16:14:22 +1000 [thread overview]
Message-ID: <m3io9v18ht.fsf@oc8180480414.ibm.com> (raw)
In-Reply-To: <1436318605-13031-2-git-send-email-sam.mj@au1.ibm.com>
Samuel Mendoza-Jonas <sam.mj@au1•ibm.com> writes:
> On powernv secondary cpus are returned to OPAL, and will then enter the
> target kernel in big-endian. However if it is set the HILE bit will persist,
> causing the first exception in the target kernel to be delivered in
> litte-endian regardless of the kernel endianess.
> Make sure that the HILE bit is switched off before entering
> kexec_sequence.
>
> Signed-off-by: Samuel Mendoza-Jonas <sam.mj@au1•ibm.com>
Discussed with Sam on IRC, this makes kexec environment the same (or at
least closer to) booting the initial payload, which is a Good Thing(TM).
The ignoring of any error from opal_reinit_cpus() (as done in this
patch) is probably a good idea as we're either running on old firmware
which doesn't have the call (in which case we'd explode no matter what)
or we're on some crazy theoretical chip that doesn't do HILE=0, in which
case this gives us the best chance for compatibility.
Reviewed-by: Stewart Smith <stewart@linux•vnet.ibm.com>
next prev parent reply other threads:[~2015-07-08 6:14 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-08 1:23 [PATCH 1/2] powerpc/kexec: Reset secondary cpu endianess before kexec Samuel Mendoza-Jonas
2015-07-08 1:23 ` [PATCH 2/2] powerpc/kexec: Reset HILE before kexec_sequence Samuel Mendoza-Jonas
2015-07-08 6:14 ` Stewart Smith [this message]
2015-07-08 2:35 ` [PATCH 1/2] powerpc/kexec: Reset secondary cpu endianess before kexec Scott Wood
2015-07-08 4:04 ` Paul Mackerras
2015-07-08 4:22 ` Scott Wood
2015-07-09 15:42 ` Segher Boessenkool
2015-07-09 20:27 ` Scott Wood
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