Subject: Re: [PATCH V2] cpuidle/powernv: Read target_residency value of idle states from DT if available

From: Stewart Smith <[email-masked]>
Date: Thu, 29 Jan 2015 09:24:33 +1100

Preeti U Murthy <[email-masked]> writes:
> On 01/28/2015 02:45 PM, Stewart Smith wrote:
>> Preeti U Murthy <[email-masked]> writes:
>>> The device tree now exposes the residency values for different idle states. Read
>>> these values instead of calculating residency from the latency values. The values
>>> exposed in the DT are validated for optimal power efficiency. However to maintain
>>> compatibility with the older firmware code which does not expose residency
>>> values, use default values as a fallback mechanism. While at it, handle some
>>> cleanups.
>> 
>> From a "I just merged the patch that exports these values from firmware"
>> point of view, using them and falling back looks good.
>> 
>> (I find the hardcoding of snooze in the driver a bit odd, as is the
>
> Snooze is the only software defined idle state, the rest are platform
> specific. The first idle state is usually associated with some sort of a
> polling operation and each architecture has a variant to this. This is
> why we end up hard-coding this idle state in the driver as far as my
> understanding goes.

At least in the PowerISA 2.07 I could only see that lowering priority
would give priority to other threads in the core, I couldn't find
anything saying that or 31,31,31 would end up saving any power... but I
could be looking in the wrong place too.

Basically, I was wanting to check that it's actually written down and
architected somewhere that this is the case and it isn't something too
P7/P8 specific.