Subject: Re: [PATCH v2 03/23] ata: sata_dwc_460ex: set dma_boundary to 0x1fff

From: Måns Rullgård <[email-masked]>
Date: Sun, 08 May 2016 22:25:39 +0100

Tejun Heo <[email-masked]> writes:

> On Tue, Apr 26, 2016 at 12:03:04PM +0300, Andy Shevchenko wrote:
>> diff --git a/drivers/ata/sata_dwc_460ex.c b/drivers/ata/sata_dwc_460ex.c
>> index 7f95389..aee8873 100644
>> --- a/drivers/ata/sata_dwc_460ex.c
>> +++ b/drivers/ata/sata_dwc_460ex.c
>> @@ -1151,7 +1151,13 @@ static struct scsi_host_template sata_dwc_sht =3D=
 {
>>  	 */
>>  	.sg_tablesize		=3D LIBATA_MAX_PRD,
>>  	/* .can_queue		=3D ATA_MAX_QUEUE, */
>> -	.dma_boundary		=3D ATA_DMA_BOUNDARY,
>> +	/*
>> +	 * Make sure a LLI block is not created that will span 8K max FIS
>> +	 * boundary. If the block spans such a FIS boundary, there is a chance
>> +	 * that a DMA burst will cross that boundary -- this results in an
>> +	 * error in the host controller.
>> +	 */
>> +	.dma_boundary		=3D 0x1fff /* ATA_DMA_BOUNDARY */,
>
> The host controller can't cross 8k boundary?  Is this for real?

>>From the manual:

  DMA block and burst transaction sizes are critical for DMA operation.
  (Also see the definition of "DMA transfer".)  These sizes should be
  selected properly to ensure error-free bus transfers. It is required
  that the DMA write burst transfer does not cross the 8192-byte Data
  FIS boundary, because the Transport Layer maintains the DMA state for
  the duration of the Data FIS transmission.

--=20
M=E5ns Rullg=E5rd