Subject: RE: [PATCH v3 2/4] net: stmmac: dwc-qos: Add FSD EQoS support

From: "Swathi K S" <[email-masked]>
Date: Thu, 6 Jun 2024 14:46:11 +0530

> -----Original Message-----
> From: Andrew Lunn [mailto:[email-masked]]
> Sent: 15 August 2023 02:17
> To: Sriranjani P <[email-masked]>
> Cc: [email-masked]; [email-masked]; [email-masked];
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> [email-masked]; [email-masked]; linux-samsung-
> [email-masked]; [email-masked]; Chandrasekar R
> <[email-masked]>; Suresh Siddha <[email-masked]>
> Subject: Re: [PATCH v3 2/4] net: stmmac: dwc-qos: Add FSD EQoS support
> 
> > +static const int rx_clock_skew_val[] = {0x2, 0x0};
> 
> > +static int dwc_eqos_setup_rxclock(struct platform_device *pdev, int
> > +ins_num) {
> > +	struct device_node *np = pdev->dev.of_node;
> > +	struct regmap *syscon;
> > +	unsigned int reg;
> > +
> > +	if (np && of_property_read_bool(np, "fsd-rx-clock-skew")) {
> > +		syscon = syscon_regmap_lookup_by_phandle_args(np,
> > +							      "fsd-rx-clock-
> skew",
> > +							      1, &reg);
> > +		if (IS_ERR(syscon)) {
> > +			dev_err(&pdev->dev,
> > +				"couldn't get the rx-clock-skew syscon!\n");
> > +			return PTR_ERR(syscon);
> > +		}
> > +
> > +		regmap_write(syscon, reg, rx_clock_skew_val[ins_num]);
> 
> Please could you explain what this is doing.

As per customer requirement, we need to provide a delay of 2ns in FSYS in
both TX and RX path and no delay in peric block

>        Andrew

Regards,
Swathi