Subject: RE: [PATCH net-next v3 6/8] net: pcs: Add 10GBASE-R mode for Synopsys Designware XPCS

From: Jiawen Wu <[email-masked]>
Date: Thu, 20 Apr 2023 17:32:05 +0800

On Thursday, April 20, 2023 4:52 PM, Vladimir Oltean wrote:
> On Thu, Apr 20, 2023 at 04:38:48PM +0800, Jiawen Wu wrote:
> > It needs to implement compat->pma_config, and add a flag in struct dw_xpcs
> > to indicate board with specific pma configuration. For 10GBASE-R interface, it
> > relatively simple, but a bit more complicate for 1000BASE-X since there are
> > logic conflicts in xpcs_do_config(), I haven't resolved yet.
> >
> > In addition, reconfiguring XPCS will cause some known issues that I need to
> > workaround in the ethernet driver. So I'd like to add configuration when I
> > implement rate switching.
> >
> > There is a piece codes for my test:
> 
> The PMA initialization procedure looks pretty clean to me (although I'm
> not clear why it depends upon xpcs->flags & DW_MODEL_WANGXUN_SP when the
> registers seem to be present in the common databook), and having it in
> the XPCS driver seems much preferable to depending on an unknown previous
> initialization stage.

The values configured in PMA depend on the board signal quality, Synopsys once
provided the values based on our board information, but we don't know the details
of the computation. So I don't think it's universal.

> 
> Could you detail a bit the known issues and the 1000BASE-X conflicts in
> xpcs_do_config()?
> 

Known issue is that traffic must be totally stopped while the PMA is being configured.
And XPCS should add a judgment that PMA only need to be reconfigured when
interface is changed.

In 1000BASE-X interface, for my current testing, PMA configuration should precede
AN configuration, and need to set PCS_DIG_CTRL1 reg? My test code for AN config:

+static int xpcs_config_aneg_c37_1000basex_wx(struct dw_xpcs *xpcs, unsigned int mode,
+					     const unsigned long *advertising)
+{
+
+	xpcs_write(xpcs, MDIO_MMD_PCS, DW_VR_MII_DIG_CTRL1, 0x3002);
+	xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, 0x0109);
+	xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, 0x0200);
+	ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1);
+	ret |= BMCR_ANENABLE;
+	xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret);
+}