From: "Jiawen Wu" <jiawenwu@trustnetic•com>
To: "'Russell King \(Oracle\)'" <linux@armlinux•org.uk>
Cc: <netdev@vger•kernel.org>, <andrew@lunn•ch>,
<hkallweit1@gmail•com>, <Jose.Abreu@synopsys•com>,
<mengyuanlou@net-swift•com>
Subject: RE: [PATCH net-next 4/7] net: pcs: xpcs: adapt Wangxun NICs for SGMII mode
Date: Mon, 31 Jul 2023 09:58:30 +0800 [thread overview]
Message-ID: <059201d9c352$810e4170$832ac450$@trustnetic.com> (raw)
In-Reply-To: <ZMOZkzCqiUZP/uQ8@shell.armlinux.org.uk>
> No there isn't, and it conforms with the above.
>
> A read looks like this:
>
> Address Data Address Data Data
> Start 10101100 000yyyyy RepeatedStart 10101101 DDDDDDDD DDDDDDDD Stop
> or Stop followed
> by Start
>
> The terms "Address" and "Data" here are as per the I²C specification.
> You will notice that the first part has one byte of address and *one*
> byte of data to convey the register address. This is what the "1" you
> are referring to above is for.
>
> For completness, a write looks like this:
>
> Address Data Data Data
> Start 10101100 000yyyyy DDDDDDDD DDDDDDDD Stop
>
> Essentially, in all cases, when 0x56 is addressed with the data
> direction in write mode, the very first byte is _always_ the register
> address and the remainder contain the data. When the data direction is
> in read mode, the bytes are always data.
>
> The description you quote above is poor because it doesn't make it
> clear whether "read" and "write" apply to the bus transactions or to
> the device operations. However, I can assure you that what is
> implemented is correct, since this is the standard small 24xx memory
> device protocol, and I've been programming that on various
> microcontrollers and such like for the last 30 years.
>
> Are you seeing a problem with the data read or written to the PHY?
You are right, I misunderstood it. :(
next prev parent reply other threads:[~2023-07-31 1:59 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-24 10:23 [PATCH net-next 0/7] support more link mode for TXGBE Jiawen Wu
2023-07-24 10:23 ` [PATCH net-next 1/7] net: pcs: xpcs: add specific vendor supoprt for Wangxun 10Gb NICs Jiawen Wu
2023-07-25 17:24 ` Andrew Lunn
2023-07-24 10:23 ` [PATCH net-next 2/7] net: pcs: xpcs: support to switch mode for Wangxun NICs Jiawen Wu
2023-07-25 17:32 ` Andrew Lunn
2023-07-26 2:40 ` Jiawen Wu
2023-07-24 10:23 ` [PATCH net-next 3/7] net: pcs: xpcs: add 1000BASE-X AN interrupt support Jiawen Wu
2023-07-24 10:23 ` [PATCH net-next 4/7] net: pcs: xpcs: adapt Wangxun NICs for SGMII mode Jiawen Wu
2023-07-24 10:34 ` Russell King (Oracle)
2023-07-25 2:05 ` Jiawen Wu
2023-07-25 7:48 ` Russell King (Oracle)
2023-07-25 9:50 ` Jiawen Wu
2023-07-25 9:58 ` Russell King (Oracle)
2023-07-25 10:08 ` Russell King (Oracle)
2023-07-25 10:45 ` Jiawen Wu
2023-07-28 10:11 ` Jiawen Wu
2023-07-28 10:24 ` Andrew Lunn
2023-07-31 1:47 ` Jiawen Wu
2023-07-28 10:33 ` Russell King (Oracle)
2023-07-31 1:58 ` Jiawen Wu [this message]
2023-08-03 2:20 ` Jiawen Wu
2023-08-03 11:10 ` Russell King (Oracle)
2023-08-04 5:56 ` Jiawen Wu
2023-07-25 17:37 ` Andrew Lunn
2023-07-26 12:14 ` Simon Horman
2023-07-24 10:23 ` [PATCH net-next 5/7] net: txgbe: support switching mode to 1000BASE-X and SGMII Jiawen Wu
2023-07-24 10:40 ` Russell King (Oracle)
2023-07-25 2:29 ` Jiawen Wu
2023-07-24 10:23 ` [PATCH net-next 6/7] net: txgbe: support copper NIC with external PHY Jiawen Wu
2023-07-24 10:43 ` Russell King (Oracle)
2023-07-25 2:41 ` Jiawen Wu
2023-07-25 8:02 ` Russell King (Oracle)
2023-07-25 10:04 ` Jiawen Wu
2023-07-25 10:38 ` Russell King (Oracle)
2023-07-26 12:15 ` Simon Horman
2023-07-24 10:23 ` [PATCH net-next 7/7] net: ngbe: move mdio access registers to libwx Jiawen Wu
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