Subject: Re: Mystery packet killing tg3

From: "Michael Chan" <[email-masked]>
Date: Tue, 03 May 2005 14:28:10 -0700

On Tue, 2005-05-03 at 15:03 -0700, David S. Miller wrote:

> Michael, there were no master/target abort bits set in the PCI status
> register from his dump.  If one of the DMA units locks up on the tg3,
> will it still be able to update the PCI_STATUS register appropriately
> when it encounters a DMA transaction error (ie. master or target abort)

I believe so. Also, the DMA read and write status registers showed all
zeros, meaning there were no DMA related errors:

DEBUG: RDMAC_MODE[000003fc] RDMAC_STATUS[00000000]
DEBUG: WDMAC_MODE[000003fc] WDMAC_STATUS[00000000]