Subject: Re: [PATCH 2/2] forcedeth: scatter gather and segmentation offload support

From: "Michael Chan" <[email-masked]>
Date: Tue, 25 Oct 2005 15:05:19 -0700

On Wed, 2005-10-26 at 01:22 +0200, Francois Romieu wrote:
> Michael Chan <[email-masked]> :
> > Please explain what did you mean by bogus?
> 
> When the CPU sets the entries of a multi-descriptor packet, the first
> descriptor is marked read while the next ones are still unset.
> 

Not sure you you meant by "marked read", but none of the new tx
descriptors will be DMA'ed by the chip until we write the producer index
and the byte seq. number.

> If any of BNX2_L2CTX_TX_HOST_{BIDX/BSEQ} prevents the asic to read
> beyond 'prod' (or b(yte)seq ?), the ordering does not matter. Right ?
> 

Right, the chip will only DMA the tx descriptors up to the (prod - 1)
index. tg3 works in a similar way.