Subject: Re: [PATCH net v1] mlxbf_gige: compute MDIO period based on i1clk

From: [email-masked]
Date: Wed, 31 Aug 2022 19:20:14 +0000

Hello:

This patch was applied to netdev/net.git (master)
by Jakub Kicinski <[email-masked]>:

On Fri, 26 Aug 2022 11:59:16 -0400 you wrote:
> This patch adds logic to compute the MDIO period based on
> the i1clk, and thereafter write the MDIO period into the YU
> MDIO config register. The i1clk resource from the ACPI table
> is used to provide addressing to YU bootrecord PLL registers.
> The values in these registers are used to compute MDIO period.
> If the i1clk resource is not present in the ACPI table, then
> the current default hardcorded value of 430Mhz is used.
> The i1clk clock value of 430MHz is only accurate for boards
> with BF2 mid bin and main bin SoCs. The BF2 high bin SoCs
> have i1clk = 500MHz, but can support a slower MDIO period.
> 
> [...]

Here is the summary with links:
  - [net,v1] mlxbf_gige: compute MDIO period based on i1clk
    https://git.kernel.org/netdev/net/c/3a1a274e933f

You are awesome, thank you!
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