Subject: Re: Route cache performance under stress

From: "David S. Miller" <[email-masked]>
Date: Mon, 09 Jun 2003 03:03:34 -0700 (PDT)

From: Andi Kleen <[email-masked]>
   Date: Mon, 9 Jun 2003 11:47:34 +0200
   
   gcc will generate a lot better code for the memsets if you can tell
   it somehow they are long aligned and a multiple of 8 bytes.

True, but the real bug is that we're initializing any of this
crap here at all.  Right now we write over the same cachelines
3 or so times.  It should really just happen once.