Subject: Re: [PATCH 20/32] rt2x00: byte ordering correctness

From: Ivo van Doorn <[email-masked]>
Date: Fri, 28 Apr 2006 17:01:32 +0200

On Friday 28 April 2006 15:46, Christoph Hellwig wrote:
> On Fri, Apr 28, 2006 at 03:42:29PM +0200, Michael Buesch wrote:
> > I guess you are confusing something here:
> > MMIO access versus values in structs (for example) that 
> > are accessed through DMA (for example).
> 
> so there's two general problems:
> 
>   mmio/pio   - linux expects the device to be le there by defalt and
>                {read,write}{b,s,l} do the switch automatically
>   dmaed data - you always need to switch data yourself, data is commonly
>   	       either be or le
> 
> now there's devices that are always be for mmio or can be switched to it
> during initialization.  For Linux you'd traditionally have to switch before
> calling {read,write}{b,s,l} or use the __raw_ version that have other issues.
> The ioread*/iowrite* APIs now have a BE version, too.

Unless I am mistaken, or the ralink design sheets are outdated on that issue,
I do recall that there was a big endian switch in one of the registers.
I think I need to definately investigate that to see if it would be usefull. :)

Thanks,

Ivo