Subject: Re: Receive side performance issue with multi-10-GigE and NUMA

From: Bill Fink <[email-masked]>
Date: Fri, 21 Aug 2009 00:00:54 -0400

On Thu, 20 Aug 2009, Ben Hutchings wrote:

> On Thu, 2009-08-20 at 03:26 -0400, Bill Fink wrote:
> > On Sat, 15 Aug 2009, Aviv Greenberg wrote:
> > 
> > > >  There may be something in the chipset
> > > 
> > > shooting in the dark: when you lspci -vvv and check the MaxPayload and
> > > MaxReadReq values for the myri devices - what are the values and are
> > > they equal? Are they the same on all your platforms?
> > 
> > IIRC, under DevCap they indicated MaxPayload 4096 bytes, and under
> > DevCtl they indicated MaxPayload 128 bytes and MaxReadReq 4096 bytes,
> > and was the same on both the Asus and SuperMicro systems.  I will
> > doublecheck tomorrow at work.  I am not clear on the meanings of
> > the different parameters.  And is DevCtl for PCI control messages
> > and DevCap for actual data transfers or something else?
> 
> DevCap is the capability register, which is read-only; DevCtl is the
> control register which holds the actual settings.
> 
> MaxPayload is the MTU and MRU for PCIe packets.  Each sub-tree of
> devices connected to a single PCIe root port needs to have MaxPayload
> set consistently.  MaxReadReq is the maximum size of any DMA read
> request.  It is a per-device setting (or possibly per-function; I
> forget).  It can be much larger than MaxPayload since read completions
> can be fragmented.

Thanks for the explanation.  I saw a BIOS setting that allowed
increasing the MaxPayload from 128 bytes to 256 bytes, and then
verified that an "lspci -vvv" then showed the DevCtl MaxPayload
to be 256 bytes.  But unfortunately it didn't help improve the
read side performance any.

						-Bill