From: Richard Cochran <richardcochran@gmail•com>
To: "Keller, Jacob E" <jacob.e.keller@intel•com>
Cc: "netdev@vger•kernel.org" <netdev@vger•kernel.org>,
"e1000-devel@lists•sourceforge.net"
<e1000-devel@lists•sourceforge.net>,
"Kirsher, Jeffrey T" <jeffrey.t.kirsher@intel•com>,
"Ronciak, John" <john.ronciak@intel•com>,
John Stultz <john.stultz@linaro•org>,
Thomas Gleixner <tglx@linutronix•de>
Subject: Re: [PATCH net V4 1/2] igb: add PTP Hardware Clock code
Date: Tue, 24 Jan 2012 18:44:07 +0100 [thread overview]
Message-ID: <20120124174405.GA2149@netboy.at.omicron.at> (raw)
In-Reply-To: <02874ECE860811409154E81DA85FBB58040BDD@ORSMSX105.amr.corp.intel.com>
On Mon, Jan 23, 2012 at 06:39:44PM +0000, Keller, Jacob E wrote:
> > +static int ptp_82576_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
> > +{
> > + u64 rate;
> > + u32 incvalue;
> > + int neg_adj = 0;
> > + struct igb_adapter *igb = container_of(ptp, struct igb_adapter, caps);
> > + struct e1000_hw *hw = &igb->hw;
> > +
> > + if (ppb < 0) {
> > + neg_adj = 1;
> > + ppb = -ppb;
> > + }
> > + rate = ppb;
> > + rate <<= 14;
> > + rate = div_u64(rate, 1953125);
> > +
>
> So is the rate ppb accumulating? I was under the impression that it
> calculated from the current clock frequency so it would need to be
> applied to the current incvalue, not the base... Is this not the
> case? What was the intention of the ppb?
The ppb is simply the desired rate offset in parts per billion. It is
not a delta from the current offset, but rather fixed from the clock's
nominal frequency. This comes from the NTP timex.freq field (but the
unit here is ppb, timex.freq is ppm with a 16 bit fraction.)
If the clock servo is a typical PI controller for example, then the
servo output already represents the accumulated offset.
> > + incvalue = 16 << IGB_82576_TSYNC_SHIFT;
> > +
> > + if (neg_adj)
> > + incvalue -= rate;
> > + else
> > + incvalue += rate;
> > +
> > + wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK));
> > +
> > + return 0;
> > +}
> > + /* Dial the nominal frequency. */
> > + wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576);
> > + break;
> > +
>
> It would be good to check whether the link speed has an impact on
> the SYSTIME register rate. I know on the 10 Gb parts the systime
> registers are driven by the DMA clock which is partitioned
> differently at slower speeds so the values have to be updated
> whenever the link speed changes..
If this is true for 82576, then it certainly is not documented. I
don't have that card, so maybe someone from Intel can answer this?
I think the documentation for the 82580 is clear about the basic rate
always being the same.
Thanks,
Richard
next prev parent reply other threads:[~2012-01-24 17:44 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-01-21 16:03 [PATCH net V4 0/2] igb: ptp hardware clock Richard Cochran
2012-01-21 16:03 ` [PATCH net V4 1/2] igb: add PTP Hardware Clock code Richard Cochran
2012-01-23 18:39 ` Keller, Jacob E
2012-01-24 17:44 ` Richard Cochran [this message]
2012-01-24 21:23 ` Keller, Jacob E
2012-01-27 19:25 ` Keller, Jacob E
2012-01-21 16:03 ` [PATCH net V4 2/2] igb: offer a PTP Hardware Clock instead of the timecompare method Richard Cochran
2012-01-23 3:57 ` [PATCH net V4 0/2] igb: ptp hardware clock Jeff Kirsher
2012-01-27 4:24 ` Jeff Kirsher
2012-01-27 10:11 ` Richard Cochran
2012-01-27 10:15 ` Jeff Kirsher
2012-01-27 10:22 ` Eric Dumazet
2012-01-27 10:56 ` Jeff Kirsher
2012-01-27 12:11 ` Richard Cochran
2012-01-27 20:42 ` Brown, Aaron F
2012-01-28 8:26 ` Richard Cochran
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