Subject: Re: net/macb: clear tx/rx completion flags in ISR

From: Steffen Trumtrar <[email-masked]>
Date: Fri, 19 Apr 2013 09:30:58 +0200

Hi Hein,

On Fri, Apr 19, 2013 at 01:13:26PM +0800, Hein Tibosch wrote:
> Hi Steffen,
> 
> > At least in the cadence IP core on the Xilinx Zynq SoC the TCOMP/RCOMP flags
> > are not auto-cleaned. As these flags are evaluated, they need to be cleaned.
> 
> This patch does not work for at least the AVR32 platform. Both RCOMP/RCOMP
> are cleared by *reading* the ISR and writing them would be fatal.
> 

:-(

> Could you tell me the version of the macb of Xilinx Zynq?
> 
>     u32 version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
>             | MACB_GREGS_VERSION;
> 
> On an AP7000 it reads as 0x0000010D
> 

This gives me 0x00000119. The TRM says it is version r1p23.

> I am thinking of making a patch like:
> 
>     if (bp->version >= xxx)
>         macb_writel(bp, ISR, MACB_BIT(TCOMP));
> 
>     if (bp->version >= xxx)
>         macb_writel(bp, ISR, MACB_BIT(RCOMP));
> 
> which would make it work on both platforms.
> 

The documentation I have is a little bit confusing in that regard.
The cadence datasheet says, this register is R/W, the Xilinx datasheet says,
it is "normaly RO", but the programming guide explicitely mentions clearing
the bit by writing to it.
It seems, that something like your patch is inevitable.

Regards,
Steffen

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